Hi Bishnu and Mitch, Thank you so much for your help! I am very sorry I did not look at that before and only focused on the tutorial which have a snapshot for RFDC config that use 245.76MHz. I have now solved the question and the ADC status is 15 with PLL working! Now I can figure out the fix point number value and try to test the ADC with signal generator.
Best regards, Yunfan 发件人: casper@lists.berkeley.edu <casper@lists.berkeley.edu> 代表 Bishnu Kumar Sharma 发送时间: 2024年2月28日 19:57 收件人: casper@lists.berkeley.edu 抄送: Yunfan ZHANG <hzzyf1...@gmail.com> 主题: Re: [casper] Question about the RFSoC Clock Configuration Hi Yunfan, I also noticed that your reference clock is 245.76 while it should be 491.52 as mentioned in the CASPER tutorial. https://casper-toolflow.readthedocs.io/projects/tutorials/en/latest/tutorials/rfsoc/platforms/rfsoc4x2.html#rf-clocking<https://urldefense.com/v3/__https:/casper-toolflow.readthedocs.io/projects/tutorials/en/latest/tutorials/rfsoc/platforms/rfsoc4x2.html*rf-clocking__;Iw!!OToaGQ!pa0jJD1ip3n7kbtzPyk31kz3pFgDDNiybC_u9Qx9BEPjtyBq3iNERqAdH6tOflZuahHXxRSn4aUwNIDM7YSI64klMZnqi2Oo$> I hope it helps. Best Regards Bishnu Kumar Sharma Institute of Astronomy and Astrophysics Academia Sinica On Thu, Feb 29, 2024 at 12:24 AM Mitchell Burnett <mitch.c.burn...@gmail.com<mailto:mitch.c.burn...@gmail.com>> wrote: Hi Yufan, Sorry this did not resolve your issues. I believe I see the issue now and am sorry I did not catch this earlier. In your previous screenshots for the configuration of the RFDC the PLL reference clock input is set to 245.76 MHz when it should be set to 491.52 MHz. The LMX file you are using, “rfsoc4x2_LMX_REF_245M76_OUT_491.52.txt”, in your init method to the RFDC is providing an output of 491.52 MHz. The input reference to the LMX is 245.76 from the LMK that provides an output reference of 491.52 to the internal PLL of the RFDC. This reference for the internal RFPLL is what is being configured in the drop down when you change it from 245.76 to 491.52.MHz. Try this and let us know how it goes for you. Best, Mitch On Feb 27, 2024, at 11:32 AM, Yunfan ZHANG <hzzyf1...@gmail.com<mailto:hzzyf1...@gmail.com>> wrote: Hi Mitch, I have switched to the m2021-dev branch for the mlib_devel and it seems that the RFDC block remains the same interface and initial configuration. Then, I did not change anything in the system clocking tab and did the same config as tutorial 2 for dual tile. The result actually remains the same, with ADC1, 2, and 4 stuck at status 6 and ADC 3 stuck at status 7. The PLL seems still not working. There is a new block which is "rfdc_V0_4". I have also tried to use that block and the log shows that this block does not fit with the RFSoC4x2 board. Best regards, Yunfan 在2024年2月21日星期三 UTC-5 11:13:58<Mitchell Burnett> 写道： Hi Yunfan, Could you please try the `m2021a-dev`<https://urldefense.com/v3/__https:/github.com/casper-astro/mlib_devel/tree/m2021a-dev__;!!OToaGQ!pa0jJD1ip3n7kbtzPyk31kz3pFgDDNiybC_u9Qx9BEPjtyBq3iNERqAdH6tOflZuahHXxRSn4aUwNIDM7YSI64klMchzn6Lv$> branch of `mlib_devel` and see if it helps resolve your issues with setting up the clock configuration? This development branch has new changes and adjustments that make simpler and straightforward in setting up the tile clocking sources. For the 4x2 board specifically, you should no longer need to make any adjustments under the “System Clocking” tab and it will be correct for the enabled ADC/DAC tiles you choose to use in your design. Hope this helps, Mitch On Feb 20, 2024, at 12:39 PM, Yunfan Zhang <yunfan...@duke.edu<mailto:yunfan...@duke.edu>> wrote: Dear CASPER Team, I really thanked for helping to solve the connection problem to the RFSoC4*2 Board for me. Now I have encounter problem using the RFDC block. I have followed the tutorial which set the sampling rate to 3932.16 Msps, Clock Out and Reference Clock 245.76 MHz. As the RFSoC 4*2, only tile 224 and tile 226 would be used. Thus, I only checked the Tile 224, 225 and 226 only. From the datasheet of the chip, I have set the clock source to ADC tile 1 (tile 225) and Tile 0, Tile 2 are both tiled to 225. Which shown like the following figures: <image001.png> <image002.png> <image003.png> <image004.png> <image005.png> However, when I check the status of the ADC, it stuck at the State 6, the PLL do not work. Is there any wrong for my configuration? I have also tried the configuration as same as the Tutorial 2, but also stuck at state 7, which PLL do not works. <image008.png><image007.png> I have also tried that the clock source directly connected to the Tile 224 and Tile 226 and do not distribute the clock from these two tiles, they both stuck at State 7, with still PLL would not working. <image006.png> Any possible solution would be great help! Best regards, Yunfan -- You received this message because you are subscribed to the Google Groups "cas...@lists.berkeley.edu<mailto:cas...@lists.berkeley.edu>" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+un...@lists.berkeley.edu<mailto:casper+un...@lists.berkeley.edu>. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/SN6PR05MB40629C078AC18D6E6C2A7092D3502%40SN6PR05MB4062.namprd05.prod.outlook.com<https://urldefense.com/v3/__https:/groups.google.com/a/lists.berkeley.edu/d/msgid/casper/SN6PR05MB40629C078AC18D6E6C2A7092D3502*40SN6PR05MB4062.namprd05.prod.outlook.com?utm_medium=email&utm_source=footer__;JQ!!OToaGQ!pa0jJD1ip3n7kbtzPyk31kz3pFgDDNiybC_u9Qx9BEPjtyBq3iNERqAdH6tOflZuahHXxRSn4aUwNIDM7YSI64klMVfJfs1v$>. <Schematic.png><Setting1.png><Setting2.png><Setting3.png><Setting4.png><Setting5.png><Result.png><Result1.png> <Screenshot.png> -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu<mailto:casper@lists.berkeley.edu>" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu<mailto:casper+unsubscr...@lists.berkeley.edu>. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/8E62C645-C324-4B73-96E4-54785D932262%40gmail.com<https://urldefense.com/v3/__https:/groups.google.com/a/lists.berkeley.edu/d/msgid/casper/8E62C645-C324-4B73-96E4-54785D932262*40gmail.com?utm_medium=email&utm_source=footer__;JQ!!OToaGQ!pa0jJD1ip3n7kbtzPyk31kz3pFgDDNiybC_u9Qx9BEPjtyBq3iNERqAdH6tOflZuahHXxRSn4aUwNIDM7YSI64klMRPTflPL$>. -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu<mailto:casper@lists.berkeley.edu>" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu<mailto:casper+unsubscr...@lists.berkeley.edu>. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CACqpYn7acUzNOcdD7aSkta-UOVtXLf4tGO8Tm%2BmwtjymKkfz3g%40mail.gmail.com<https://urldefense.com/v3/__https:/groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CACqpYn7acUzNOcdD7aSkta-UOVtXLf4tGO8Tm*2BmwtjymKkfz3g*40mail.gmail.com?utm_medium=email&utm_source=footer__;JSU!!OToaGQ!pa0jJD1ip3n7kbtzPyk31kz3pFgDDNiybC_u9Qx9BEPjtyBq3iNERqAdH6tOflZuahHXxRSn4aUwNIDM7YSI64klMTYCa6FD$>. -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/SN6PR05MB4062F776ADEEE5207750DF63D35F2%40SN6PR05MB4062.namprd05.prod.outlook.com.
