Hi Laura,
For FPGA utilization, I look at the file:
sysgen/synth_model/modelfilename_cw.syr
Mark
On Wed, Nov 18, 2009 at 2:26 PM, Laura Spitler wrote:
> Hi everyone,
>
> I have a general question about over mapping a design. What's the
> easiest way to determine by how much I've over utilized
Hi Laura,
At least with 7.1, the output of system generator includes a log file
that gives some rough usage numbers. The IO will always be overmapped
in these reports because all of the connections for shared registers
and brams and such are considered IO pins, but you may be able to get
some usefu
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