On Tue, Apr 19, 2022 at 11:18:07AM -0400, Chris Zach via cctalk wrote:
Wonder if there is a SPARC build. Guess it's too much to ask if it
will run on my Sun 386i's
There is, but the hardware support does exclude a lot of "hobbyist"
SPARC systems[1]:
"Oracle Solaris 11.4 supports systems bas
> On Apr 19, 2022, at 3:38 PM, John Foust via cctalk
> wrote:
>
> At 01:40 PM 4/19/2022, Bjoren Davis via cctalk wrote:
>> Looking at the photo I see the name "Dave Iacobone". I wonder if he is
>> still around and remembers that board.
>
> https://www.linkedin.com/in/dave-iacobone-0a11436
Maybe a different guy, since Pro development was in the late 1970s to early
1980s.
paul
Probably. Still would be interesting to see what the board actually
is/does, I wondered why they never did DMA transfers for the Pro, maybe
being a single user system it was pretty much pointless
> On Apr 20, 2022, at 1:37 PM, Chris Zach via cctalk
> wrote:
>
>> Maybe a different guy, since Pro development was in the late 1970s to early
>> 1980s.
>> paul
>
> Probably. Still would be interesting to see what the board actually is/does,
> I wondered why they never did DMA transfe
At 12:27 PM 4/20/2022, Paul Koning wrote:
>Maybe a different guy, since Pro development was in the late 1970s to early
>1980s.
Perhaps his son? Or the guy returned to DEC, or listed his career
differently on LinkedIn for other reasons? It's not a common name.
- John
I don't know it for certain, but I am pretty sure that it is true that
virtually all controllers issue the commands in this sequence, Set Cylinder,
Set Head and then Seek, or words to that effect.
They then wait for Ready which can be 10's of milliseconds later. So there is
plenty of time to loa
On Wed, 20 Apr 2022, Tom Gardner via cctalk wrote:
Likewise, I don't know it for certain, but I am pretty sure that it is
true that virtually all controllers switch heads sequentially when
transferring blocks beyond the end of the track,
Are you implying that data/file that is more than one tr
Guy,
I agree that accessing data in blockram (synchronous with fixed latency) is
really easier than accessing it from RAM (asynchronous with variable latency).
Anyway I'm weighting the "cost" of additional complexity, which in change would
allow to spare on Zynq cost.
In any case memory access is
I'm using Zynq SOMs (System on a module) that will plug into a "base
board" (with hilrose connectors). It is the base board that will have
the "personality" of the emulator. The baseboard will be fairly simple
(level shifters, a small bit of logic and the drive interface
transceivers). So th
