On 7/10/18 2:38 PM, Noel Chiappa via cctalk wrote:
> From: Jerry Weiss
> See http://simh.trailing-edge.com/semi/j11.html for information on the
> design of the J11.
Thanks for that pointer; I don't think I've ever seen that - quite
interesting.
Alas, it didn't have the cache
On Tue, Jul 10, 2018 at 1:38 PM, Noel Chiappa via cctalk <
cctalk@classiccmp.org> wrote:
> > From: Jerry Weiss
> > In addition to above, there is a bypass cache bit in the PDR (section
> > 1.5.6.2) for finer control.
>
> Yes, I only found that out last night (or maybe I saw it on a
On 10/07/18 11:01, Noel Chiappa via cctalk wrote:
I suppose only someone who worked on the DCJ11 would know; but I have no idea
how to track down such a person.
Not sure that I know such a person but you might try hunting for the
Semiconductor Databook Volume 1 1987.
It has some basic
> From: Jerry Weiss
> See http://simh.trailing-edge.com/semi/j11.html for information on the
> design of the J11.
Thanks for that pointer; I don't think I've ever seen that - quite
interesting.
Alas, it didn't have the cache info - but now that I've though about it
overnight, I'm
On 7/10/18 5:01 AM, Noel Chiappa via cctalk wrote:
So, if one looks up the Cache Control Register in, say, the KDJ11-A
(EK-KDJ1A-UG-002), one sees (in section 1.6.2.1) that there are _three_ ways
to disable the cache: bits 2, 3 ('force miss'), and 9 ('bypass cache').
Looking at the DCJ11 manual
