On 11/28/17 13:27, emanuel stiebler via cctalk wrote:
> Dave has a KV10 already in verilog, so why not port it to the uengine?
Well, the uengine would have to be considerably modified before it could be
used for a PDP-10 (e.g. wider data-paths); this version is very specialized
to the SD
On 2017-11-28 08:54, Noel Chiappa via cctalk wrote:
and the whole thing is here:
https://github.com/dabridgham/QSIC
including the Verilog for the uengine. Dave reports that it should be easy to
adapt his uengine design to other uses, it should run in pretty much any
FPGA. So if you want to
