Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

That'll be me, I guess, It's in VHDL. URL in sig. On 10/07/16 15:21, Paul Birkel wrote: -Original Message- From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Guy Sotomayor Jr Sent: Monday, June 20, 2016 4:04 PM To: General Discussion: On-Topic and Off-Topic Posts Subject:

Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

And Carl Claunch has an IBM 1130 in VHDL. Marc Sent from my iPad > On Jul 10, 2016, at 10:23 PM, Lawrence Wilkinson wrote: > > That'll be me, I guess, It's in VHDL. URL in sig. > >> On 10/07/16 15:21, Paul Birkel wrote: >> -Original Message- >> From: cctalk [mailto:cctalk-boun...@class

Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

And I'm very close to having a 360/65 in VHDL. Op 11 jul. 2016 2:44 a.m. schreef "Curious Marc" : > And Carl Claunch has an IBM 1130 in VHDL. > Marc > > Sent from my iPad > > > On Jul 10, 2016, at 10:23 PM, Lawrence Wilkinson > wrote: > > > > That'll be me, I guess, It's in VHDL. URL in sig. > >

RE: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

-Original Message- From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Camiel Vanderhoeven Sent: Monday, July 11, 2016 4:31 AM To: General Discussion: On-Topic and Off-Topic Posts Subject: Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?) And

Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

No kidding! That's a massive effort. How close is that to a 360/50? I have a front panel that needs a brain, could sure use that! Marc Sent from my iPhone > On Jul 11, 2016, at 5:31 PM, Camiel Vanderhoeven wrote: > > And I'm very close to having a 360/65 in VHDL. > Op 11 jul. 2016 2:44 a.m. sc

Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

On 7/11/16 1:31 AM, Camiel Vanderhoeven wrote: > And I'm very close to having a 360/65 in VHDL. > Op 11 jul. 2016 2:44 a.m. schreef "Curious Marc" : > Was the microcode derived from the engineering drawings? >From memory, the 65 is the bigger brother to the 50 with a wider memory bus. It was a

Re: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

> > And I'm very close to having a 360/65 in VHDL. > > Was the microcode derived from the engineering drawings? Yes, from hand-corrected OCR scans. To be precise, the ALDs and microcode I'm using are not for a plain 2065, but for a 7201-02, the variant that was used in the 9020 complex. I'm makin

RE: IBM 360/30 in verilog (was: How do they make Verilog code for unknown ICs?)

> And I'm very close to having a 360/65 in VHDL. > - > > Sweet :->. What FPGA platform are you using? Lawrence used a Spartan 3. Don't know how close to "full" he pushed it. I'm using the XUPV5 PCIE board (Xilinx Virtex-5 XC5VLX110T); currently about 60% occupied, but the design needs lots