On 12/05/2016 08:51 AM, Mouse wrote:
>
> Little- and big-endian do this; conversion between them is
> byteswapping, which is self-inverse. Conversion between
> PDP11-endian (0x87654321 stored as 0x65 0x87 0x21 0x43) and either
> big- or little-endian is also self-inverse. Is there any hardware
On 12/05/2016 12:17 PM, Chuck Guzis wrote:
> Or how about architectures not using a word length that's an integral
> number of bytes?
You mean like any 36-bit machine?
On 12/05/2016 11:51 AM, Mouse wrote:
>> Middle-endian FTW
> That makes me wonder: was there any hardware that used an endianness
> such that conversion didn't loop with period 2?
Not quite the same thing but weren't longwords on the PDP-11
little-endian for the bytes within the word but big-e
> -Original Message-
> From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of David
> Bridgham
> Sent: 05 December 2016 18:37
> To: General Discussion: On-Topic and Off-Topic Posts
>
> Subject: Re: Odd "endianness" [was Re: RE: Base 64 posts to the
t;
> > Subject: Re: Odd "endianness" [was Re: RE: Base 64 posts to the list]
> >
> > On 12/05/2016 12:17 PM, Chuck Guzis wrote:
> >
> > > Or how about architectures not using a word length that's an integral
> > > number of bytes?
>
On 12/05/2016 10:37 AM, David Bridgham wrote:
> On 12/05/2016 12:17 PM, Chuck Guzis wrote:
>
>> Or how about architectures not using a word length that's an
>> integral number of bytes?
>
> You mean like any 36-bit machine?
Or any 12 or 60 bit machine.
--Chuck
>> Or how about architectures not using a word length that's an
>> integral number of bytes?
> You mean like any 36-bit machine?
No, they usually either ran as 6 6-bit bytes or 4 9-bit bytes, from
what I understand. (The era of 36-bit machines was before "byte" had
drifted to its current synonymi
>>> Middle-endian FTW
>> That makes me wonder: was there any hardware that used an endianness
>> such that conversion didn't loop with period 2?
> Not quite the same thing but weren't longwords on the PDP-11
> little-endian for the bytes within the word but big-endian for words
> within the lon
Charles Anthony wrote:
> PDP-10: 36 bit word, 5*7bit characters.
Mouse wrote:
>> You mean like any 36-bit machine?
> No, they usually either ran as 6 6-bit bytes or 4 9-bit bytes, from
> what I understand.
As Charles wrote, the PDP-10 commonly uses 7-bit bytes for ASCII text,
but that's only part
On 12/05/2016 01:09 PM, Lars Brinkhoff wrote:
> As Charles wrote, the PDP-10 commonly uses 7-bit bytes for ASCII
> text, but that's only part of the truth. The architecture is quite
> byte size agnostic. There are instructions to operate on any byte
> size from 1 to 36 bits, at any position insi
From: Chuck Guzis
Sent: Monday, December 05, 2016 6:15 PM
> On 12/05/2016 01:09 PM, Lars Brinkhoff wrote:
>> As Charles wrote, the PDP-10 commonly uses 7-bit bytes for ASCII
>> text, but that's only part of the truth. The architecture is quite
>> byte size agnostic. There are instructions to op
On 12/07/2016 12:46 PM, Rich Alderson wrote:
> Neither of those is entirely accurate. 9-track tapes on the PDP-10
> used one of the following encodings:
The last time that I had to deal with PDP-10 tapes, admittedly also 40
years ago was essentially core-dump format. 5 7-bit characters per
word
On 12/7/2016 10:42 PM, Chuck Guzis wrote:
On 12/07/2016 12:46 PM, Rich Alderson wrote:
Neither of those is entirely accurate. 9-track tapes on the PDP-10
used one of the following encodings:
The last time that I had to deal with PDP-10 tapes, admittedly also 40
years ago was essentially cor
Rich Alderson wrote:
> From: Chuck Guzis
> Sent: Monday, December 05, 2016 6:15 PM
>> I've seen PDP-10 9-track tapes done two ways--one character per frame
>> and then 4 frames (36 bits) with 5 7-bit characters and the sign bit
>> left over.
>
> Neither of those is entirely accurate. 9-track tapes
On 12/07/2016 11:03 PM, jim stephens wrote:
> The Multics version I saw came from a Fortran version taken from a
> PDP10. If I'm not mistaken it was directly from the timeshare
> system they used in Billerica,Ma where Don Woods worked. After some
> massaging it was unleashed on Multics. Most o
> From: Rich Alderson
> 9-track tapes on the PDP-10 used one of the following encodings:
What about 7-track, any idea? I would assume 6 x 6-bit tape frames per 36-bit
word, but that's just a guess.
Noel
From: cctalk on behalf of Noel Chiappa
Sent: Thursday, December 8, 2016 1:30:48 PM
To: cctalk@classiccmp.org
Cc: j...@mercury.lcs.mit.edu
Subject: Re: Odd "endianness" [was Re: RE: Base 64 posts to the list]
> From: Rich Alderson
> 9-track tapes on the PDP-10
On 12/08/2016 05:08 PM, dwight wrote:
> Not meaning to throw things to far off but on my
>
> NC4000 machine( 16 bit ), I found ByteSwap useful enough that I had it
>
> hard wired.
>
> I have an old computer that was intended to do FFTs. It has a
>
> complete bit order swap, MSB to LSB, instruct
> > I have an old computer that was intended to do FFTs. It has a
> > complete bit order swap, MSB to LSB, instruction.
>
> Well, there's the PowerPC "endian" mode (settable in the MSR)--but it's
> just "sort of"--the little-endian mode simply XORs the lower 3 bits of
> the address with 111 (i.e.
From: Chuck Guzis
Sent: Wednesday, December 07, 2016 10:43 PM
> On 12/07/2016 12:46 PM, Rich Alderson wrote:
>> Neither of those is entirely accurate. 9-track tapes on the PDP-10
>> used one of the following encodings:
> The last time that I had to deal with PDP-10 tapes, admittedly also 40
> y
On 12/08/2016 08:46 PM, Cameron Kaiser wrote:
>>> I have an old computer that was intended to do FFTs. It has a
>>> complete bit order swap, MSB to LSB, instruction.
>>
>> Well, there's the PowerPC "endian" mode (settable in the MSR)--but
>> it's just "sort of"--the little-endian mode simply XORs
On Thu, Dec 8, 2016 at 9:51 AM, Chuck Guzis wrote:
> On 12/07/2016 11:03 PM, jim stephens wrote:
>
>
>
> I must have the wrong mindset. Does computer chess hold any interest
> today? Or is the matter of machine-over-human pretty much a fait accompli?
>
> --Chuck
>
>
I'll run thru some moves wit
Rich Alderson writes:
> The 5 characters per word is irrelevant to a discussion of tape, whether
> 9- or 7-track: That's how ASCII text was represented in memory, on disk,
> on DECtape, or on any other word-oriented medium. Representing the bits
> in an ASCII character by the character itself (t
> On Dec 9, 2016, at 1:25 AM, Chuck Guzis wrote:
>
> On 12/08/2016 08:46 PM, Cameron Kaiser wrote:
I have an old computer that was intended to do FFTs. It has a
complete bit order swap, MSB to LSB, instruction.
>>>
>>> Well, there's the PowerPC "endian" mode (settable in the MSR)--bu
r.
Dwight
From: cctalk on behalf of jim stephens
Sent: Thursday, December 8, 2016 10:48:05 PM
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: Odd "endianness" [was Re: RE: Base 64 posts to the list]
On Thu, Dec 8, 2016 at 9:51 AM, Chuck Guzis wrote:
>
Rich Alderson wrote:
> There are also Two-Word Global Byte Pointers (which I've never seen
> abbreviated) which carry the standard "any size byte at any position"
Maybe they were just Global Byte Pointers? OWG's were a late
addition. I was a member of the FORTRAN-10/20 v10 project to make it
gen
On 12/09/2016 07:02 AM, Paul Koning wrote:
> Rather than "can't make up their mind", a good reason to have
> selectable endian processors is that the best choice may depend on
> the application. So for embedded systems in particular, it's good to
> be able to pick which you want.
My quip was an
On 12/08/2016 07:08 PM, dwight wrote:
Not meaning to throw things to far off but on my
NC4000 machine( 16 bit ), I found ByteSwap useful enough that I had it
hard wired.
I have an old computer that was intended to do FFTs. It has a
complete bit order swap, MSB to LSB, instruction.
Yup, thi
From: Phil Budne
Sent: Friday, December 09, 2016 10:44 AM
> Rich Alderson wrote:
>> There are also Two-Word Global Byte Pointers (which I've never seen
>> abbreviated) which carry the standard "any size byte at any position"
> Maybe they were just Global Byte Pointers? OWG's were a late
> addit
> Both One-Word and Two-Word Global Byte Pointers were added at the same
> time as extended addressing, according to the HRM. Simple "Global Byte
> Pointer" would have been inherently ambiguous.
OWG's were added to the KL ucode later:
;251ADD CODE FOR ONE WORD GLOBAL BYTE POINTERS.
; TO
On Fri, Dec 9, 2016 at 12:47 PM, Rich Alderson
wrote:
> [1] For non-PDP10 programmers: The original architecture of the PDP-6 and
> PDP-10 used an 18-bit (256KW) address space. The KI-10 processor added
> a 22-bit pager and a concept of sections to the hardware.
>
As you say, the KI10
From: Eric Smith
Sent: Saturday, December 10, 2016 6:38 PM
> On Fri, Dec 9, 2016 at 12:47 PM, Rich Alderson
> wrote:
>> [1] For non-PDP10 programmers: The original architecture of the PDP-6
>> and PDP-10 used an 18-bit (256KW) address space. The KI-10
>> processor added a 22-bit pager
Noel Chiappa wrote:
> > 9-track tapes on the PDP-10 used one of the following encodings:
>
> What about 7-track, any idea? I would assume 6 x 6-bit tape frames per
> 36-bit word, but that's just a guess.
A reasonable guess, and one I'd make too. But I don't know either.
Supposedly, many ITS
From: Lars Brinkhoff
Sent: Wednesday, December 14, 2016 3:54 AM
> Noel Chiappa wrote:
>>> 9-track tapes on the PDP-10 used one of the following encodings:
>> What about 7-track, any idea? I would assume 6 x 6-bit tape frames per
>> 36-bit word, but that's just a guess.
> A reasonable guess, and
Here's a tickler for the list...
I've used bit-addressable machines, where individual bits were directly
addressed without regard to their position within a byte or word. E.g.,
a system with 48 bit addresses, where the lower 3 bits of an address
specified the bit within a byte; the next 3 specifi
On Sat, Dec 17, 2016 at 2:59 PM, Chuck Guzis wrote:
> What perplexed me is that the address of 0 0 specified the first
> bit in byte 0 of word 0, but that same bit was the *high order* bit in
> the corresponding byte and word. It would seem to make more sense
> reversing the significance of
On 12/17/2016 05:50 PM, Eric Smith wrote:
>
> The TI TMS34010 and TMS34020 graphics processors were
> bit-addressable, though instructions had to be 16-bit aligned. The
> TMS34010 and the default mode of the TMS34020 were little-endian,
> with bit 0 being the least significant bit. The TMS34020 h
37 matches
Mail list logo
