> I don't know if the front console on the early UNIBUS machines works without
> any memory on the UNIBUS - I'm too lazy to check. I have this vague memory
> that
> they do, though.
The front console on the '45 indeed does run just fine with no UNIBUS (or
FASTBUS) memory in the machine. Its is
> From: Brent Hilpert
> I wouldn't have thought any of the (various 11 CPU) ODTs used
> interrupts for the console
They don't.
> Don't know which CPU Noel was referring to.
The OP was having problems with an LSI-11 (M7264 quad card); I was working
with an LSI-11/2 (M7270 dual
> From: Allison Parent
> ! Seriously? ... Memory of some form there is a must.
I don't know about you, but my approach in looking into hardware issues is
often to start by reducing things to the simplest possible configuration that
exhibits the failure.
(I asssume the various reasons
On 2019-Aug-14, at 1:26 PM, Allison Parent via cctalk wrote:
> IPhoned it in!
>
>> On Aug 14, 2019, at 2:19 PM, Noel Chiappa via cctalk
>> wrote:
>>
>> From: Jonathan (systems_glitch)
>
>> Yep, fun times on LSI-11/2!
>
> Heh, this one was _utterly trivial_ compared to the 'must have working
IPhoned it in!
> On Aug 14, 2019, at 2:19 PM, Noel Chiappa via cctalk
> wrote:
>
> From: Jonathan (systems_glitch)
> Yep, fun times on LSI-11/2!
Heh, this one was _utterly trivial_ compared to the 'must have working memory
at 0 or ODT won't start'! (I don't think I've ever seen that one
> From: Jonathan (systems_glitch)
> Yep, fun times on LSI-11/2!
Heh, this one was _utterly trivial_ compared to the 'must have working memory
at 0 or ODT won't start'! (I don't think I've ever seen that one in DEC
documentation anywhere...)
Noel
On 8/14/2019 10:17 AM, Noel Chiappa via cctalk wrote:
> From: Paul Koning
> Isn't the interrupt disabled by RESET?
Nope. On the -11/03 and KDF11-A, BEVNT is wired straight into the CPU, and
there's no internal register to control it.
The BDV11 does have a register which can
Yep, fun times on LSI-11/2! Some configurations also won't boot unless it's
on, if I remember correctly. I suppose this is part of the reason that
LSI-11/2 CPU boards are so cheap!
Thanks,
Jonathan
On Wed, Aug 14, 2019 at 10:17 AM Noel Chiappa via cctalk <
cctalk@classiccmp.org> wrote:
> >
> From: Paul Koning
> Isn't the interrupt disabled by RESET?
Nope. On the -11/03 and KDF11-A, BEVNT is wired straight into the CPU, and
there's no internal register to control it.
The BDV11 does have a register which can enable/disable the LTC (it connects
BEVNT to ground via a
> On Aug 14, 2019, at 7:31 AM, Noel Chiappa via cctalk
> wrote:
>
>> From: Jerry Weiss
>
>> I turned BEVENT off and it boots successfully. I am not immediately
>> sure why this is necessary.
>
> If an LTC interrupt happens before the OS has set up the LTC vector, etc,
> hilarity ensues.
>
> From: Jerry Weiss
> I turned BEVENT off and it boots successfully. I am not immediately
> sure why this is necessary.
If an LTC interrupt happens before the OS has set up the LTC vector, etc,
hilarity ensues.
E.g. the LTC has to be turned off before UNIX V6 will boot on an -11/23:
That sounds like it is trapping due to an LTC interrupt. Turn off the LTC
cheers,
Nigel
On 13/08/2019 21:05, Douglas Taylor via cctalk wrote:
Recently, I assembled one of the RX02 emulator boards developed by
AK6DN. I am using it presently in a BA11-M box with PDP-11/2 cpu
(really basic 16
There are two versions of XXDP+ V2 monitors. The XXDPSM.SYS is needed
for cpu's w/o MMU's or don't have more than 28KW. This and XXDPXM.SYS
are both on the AK6DN diagnostic image. However, only a few other
programs exist on the image.
In SIMH the AK6DN image does the same thing. The halt
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