r365305 - [RISCV] Specify registers used for exception handling

Author: asb Date: Mon Jul 8 02:38:06 2019 New Revision: 365305 URL: http://llvm.org/viewvc/llvm-project?rev=365305&view=rev Log: [RISCV] Specify registers used for exception handling Implements the handling of __builtin_eh_return_regno(). Differential Revision: https://reviews.llvm.org/D63417 P

r365329 - [RISCV][NFC] Make use of Triple::isRISCV

Author: asb Date: Mon Jul 8 08:07:12 2019 New Revision: 365329 URL: http://llvm.org/viewvc/llvm-project?rev=365329&view=rev Log: [RISCV][NFC] Make use of Triple::isRISCV Use new helper introduced in rL365327. Modified: cfe/trunk/lib/Driver/ToolChains/Gnu.cpp cfe/trunk/lib/Driver/ToolCha

Re: r365825 - [clang-shlib] Fix clang-shlib for PRIVATE dependencies

On Thu, 11 Jul 2019 at 22:20, Shoaib Meenai via cfe-commits wrote: > > Author: smeenai > Date: Thu Jul 11 14:20:38 2019 > New Revision: 365825 > > URL: http://llvm.org/viewvc/llvm-project?rev=365825&view=rev > Log: > [clang-shlib] Fix clang-shlib for PRIVATE dependencies > > Any static library wit

r366450 - [RISCV] Hard float ABI support

Author: asb Date: Thu Jul 18 08:33:41 2019 New Revision: 366450 URL: http://llvm.org/viewvc/llvm-project?rev=366450&view=rev Log: [RISCV] Hard float ABI support The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using

r366454 - Revert "[RISCV] Hard float ABI support" r366450

Author: asb Date: Thu Jul 18 09:13:17 2019 New Revision: 366454 URL: http://llvm.org/viewvc/llvm-project?rev=366454&view=rev Log: Revert "[RISCV] Hard float ABI support" r366450 The commit was missing a few hunks. Will fix and recommit. Removed: cfe/trunk/test/CodeGen/riscv32-ilp32d-abi.c

Re: r366450 - [RISCV] Hard float ABI support

t the F > instruction set extension (ignoring target-abi) > ^ > :1:93: note: possible intended match here > Hard-float 'f' ABI can't be used for a target that doesn't support the F > instruction set extension (ignoring target-abi) > > > > On Thu, Jul 1

r366480 - [RISCV] Hard float ABI support

Author: asb Date: Thu Jul 18 11:29:59 2019 New Revision: 366480 URL: http://llvm.org/viewvc/llvm-project?rev=366480&view=rev Log: [RISCV] Hard float ABI support The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using

[clang] 3dcfd48 - [CodeGen] Increase applicability of ffine-grained-bitfield-accesses for targets with limited native integer widths

Author: Alex Bradbury Date: 2020-06-12T10:33:47+01:00 New Revision: 3dcfd482cb17fad2d641c976b822d1fe36dc1359 URL: https://github.com/llvm/llvm-project/commit/3dcfd482cb17fad2d641c976b822d1fe36dc1359 DIFF: https://github.com/llvm/llvm-project/commit/3dcfd482cb17fad2d641c976b822d1fe36dc1359.diff

r332222 - [RISCV][NFC] Use more appropriate label for CHECK lines

Author: asb Date: Mon May 14 02:14:43 2018 New Revision: 33 URL: http://llvm.org/viewvc/llvm-project?rev=33&view=rev Log: [RISCV][NFC] Use more appropriate label for CHECK lines 'CC1' was a misleading prefix. Committing so as to simplify the diff for a patch I'm about to put up for revie

r321693 - Update clang cc1as for createMCAsmBackend change in r321692

Author: asb Date: Wed Jan 3 00:53:24 2018 New Revision: 321693 URL: http://llvm.org/viewvc/llvm-project?rev=321693&view=rev Log: Update clang cc1as for createMCAsmBackend change in r321692 Modified: cfe/trunk/tools/driver/cc1as_main.cpp Modified: cfe/trunk/tools/driver/cc1as_main.cpp URL:

r322276 - [RISCV] Add the RISCV target and compiler driver

Author: asb Date: Thu Jan 11 05:36:56 2018 New Revision: 322276 URL: http://llvm.org/viewvc/llvm-project?rev=322276&view=rev Log: [RISCV] Add the RISCV target and compiler driver As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver support (RV64 to follow). Differentia

r322277 - [Driver][RISCV] Fix r322276 by adding missing dummy crtbegin.o files to test input

Author: asb Date: Thu Jan 11 05:51:06 2018 New Revision: 322277 URL: http://llvm.org/viewvc/llvm-project?rev=322277&view=rev Log: [Driver][RISCV] Fix r322276 by adding missing dummy crtbegin.o files to test input The dummy crtbegin.o files were left out in r322276 (as they were ignored by svn a

r322286 - [Driver][RISCV] Fix r322276 for Windows (path separator issue)

Author: asb Date: Thu Jan 11 07:38:01 2018 New Revision: 322286 URL: http://llvm.org/viewvc/llvm-project?rev=322286&view=rev Log: [Driver][RISCV] Fix r322276 for Windows (path separator issue) We were seeing test failures of riscv32-toolchain.c on windows due to the \ path separator being used f

r322294 - [Driver][RISCV] Another Windows file separator fix for riscv32-toolchain.c test

Author: asb Date: Thu Jan 11 09:06:32 2018 New Revision: 322294 URL: http://llvm.org/viewvc/llvm-project?rev=322294&view=rev Log: [Driver][RISCV] Another Windows file separator fix for riscv32-toolchain.c test I've checking the failure log, this _should_ be the last one. Sorry for not spotting t

r322396 - Refactor handling of signext/zeroext in ABIArgInfo

Author: asb Date: Fri Jan 12 12:08:16 2018 New Revision: 322396 URL: http://llvm.org/viewvc/llvm-project?rev=322396&view=rev Log: Refactor handling of signext/zeroext in ABIArgInfo As @rjmccall suggested in D40023, we can get rid of ABIInfo::shouldSignExtUnsignedType (used to handle cases like t

r322435 - Fix test/Driver/riscv32-toolchain.c for builds setting CLANG_DEFAULT_LINKER

Author: asb Date: Sat Jan 13 01:21:11 2018 New Revision: 322435 URL: http://llvm.org/viewvc/llvm-project?rev=322435&view=rev Log: Fix test/Driver/riscv32-toolchain.c for builds setting CLANG_DEFAULT_LINKER Petr Hosek reported an external buildbot was failing on riscv32-toolchain.c, seemingly as

r322494 - [RISCV] Implement RISCV ABI lowering

Author: asb Date: Mon Jan 15 09:54:52 2018 New Revision: 322494 URL: http://llvm.org/viewvc/llvm-project?rev=322494&view=rev Log: [RISCV] Implement RISCV ABI lowering RISCVABIInfo is implemented in terms of XLen, supporting both RV32 and RV64. Unfortunately we need to count argument registers in

r322514 - [RISCV] Fix test failures on non-assert builds introduced in r322494

Author: asb Date: Mon Jan 15 12:45:15 2018 New Revision: 322514 URL: http://llvm.org/viewvc/llvm-project?rev=322514&view=rev Log: [RISCV] Fix test failures on non-assert builds introduced in r322494 Thanks to Eli Friedman, who suggested the reason these tests failed on a few buildbots yet works

Re: r322769 - [RISCV] Propagate -mabi and -march values to GNU assembler.

On 18 January 2018 at 00:38, Rafael Avila de Espindola via cfe-commits wrote: > With this I am getting a test failure on linux: > > TEST 'Clang :: Driver/riscv-gnutools.c' FAILED > > Script: > -- > /home/admin/llvm/build/bin/clang -target riscv32-linux-un

r324170 - [RISCV] Create a LinuxTargetInfo when targeting Linux

Author: asb Date: Sat Feb 3 03:56:11 2018 New Revision: 324170 URL: http://llvm.org/viewvc/llvm-project?rev=324170&view=rev Log: [RISCV] Create a LinuxTargetInfo when targeting Linux Previously, RISCV32TargetInfo or RISCV64TargetInfo were created unconditionally. Use LinuxTargetInfo to ensure t

r357693 - [RISCV][NFC] s/riscv32-linux-unknown-elf/riscv32-unknown-linux-gnu in test/Driver/riscv32-toolchain.c

Author: asb Date: Thu Apr 4 06:51:41 2019 New Revision: 357693 URL: http://llvm.org/viewvc/llvm-project?rev=357693&view=rev Log: [RISCV][NFC] s/riscv32-linux-unknown-elf/riscv32-unknown-linux-gnu in test/Driver/riscv32-toolchain.c riscv32-linux-unknown-elf was a weird thing to test for as it do

r357699 - [RISCV] Collect library directories and triples for riscv64 triple too

Author: asb Date: Thu Apr 4 07:18:26 2019 New Revision: 357699 URL: http://llvm.org/viewvc/llvm-project?rev=357699&view=rev Log: [RISCV] Collect library directories and triples for riscv64 triple too When setting up library and tools paths when detecting an accompanying GCC installation only ris

r357702 - [RISCV] Fix rL357699 by adding missing zero-length files

Author: asb Date: Thu Apr 4 07:36:07 2019 New Revision: 357702 URL: http://llvm.org/viewvc/llvm-project?rev=357702&view=rev Log: [RISCV] Fix rL357699 by adding missing zero-length files svn add doesn't play very nicely here... Added: cfe/trunk/test/Driver/Inputs/basic_riscv64_tree/lib/gcc/

r357989 - [RISCV][NFC] Refactor RISC-V ABI lowering tests in preparation for hard float patches

Author: asb Date: Tue Apr 9 03:12:49 2019 New Revision: 357989 URL: http://llvm.org/viewvc/llvm-project?rev=357989&view=rev Log: [RISCV][NFC] Refactor RISC-V ABI lowering tests in preparation for hard float patches Split tests in to files representing the subset of RISC-V ABIs they should have

r357991 - [RISCV][NFC] Minor fixup for r357989

Author: asb Date: Tue Apr 9 03:25:05 2019 New Revision: 357991 URL: http://llvm.org/viewvc/llvm-project?rev=357991&view=rev Log: [RISCV][NFC] Minor fixup for r357989 One of the tests in riscv64-lp64-lp64f-lp64d would have had a different lowering for lp64f/lp64d as a float argument was missed.

r357993 - [RISCV] Unbreak test from r357989

Author: asb Date: Tue Apr 9 03:44:47 2019 New Revision: 357993 URL: http://llvm.org/viewvc/llvm-project?rev=357993&view=rev Log: [RISCV] Unbreak test from r357989 There were some errors in the committed test checks, left in due to a git stash apply mishap. Modified: cfe/trunk/test/CodeGen/

r348929 - [clang-fuzzer] Add explicit dependency on clangSerialization for clangHandleCXX after rC348907

Author: asb Date: Wed Dec 12 06:33:24 2018 New Revision: 348929 URL: http://llvm.org/viewvc/llvm-project?rev=348929&view=rev Log: [clang-fuzzer] Add explicit dependency on clangSerialization for clangHandleCXX after rC348907 This library was breaking my -DBUILD_SHARED_LIBS=1 build. rC348915 seem

Re: r348915 - Add explicit dependency on clangSerialization for a bunch of components to fix -DBUILD_SHARED_LIBS=on build

On Wed, 12 Dec 2018 at 08:05, Fangrui Song via cfe-commits wrote: > > Author: maskray > Date: Wed Dec 12 00:02:18 2018 > New Revision: 348915 > > URL: http://llvm.org/viewvc/llvm-project?rev=348915&view=rev > Log: > Add explicit dependency on clangSerialization for a bunch of components to > fix

Re: [llvm-dev] Upgrading phabricator

On 30 September 2016 at 14:21, Eric Liu via llvm-commits wrote: > Thanks for the feedback Aaron! :) > > I've disabled it. I think the annoying part really is the status (e.g. > Request, Closed etc) in the tag, and I am wondering if a tag with just line > numbers like "(N Loc)" would be better. But

[clang] 1ecf120 - [index-while-building] Fix build with -DBUILD_SHARED_LIBS=True

Author: Alex Bradbury Date: 2020-08-20T15:12:56+01:00 New Revision: 1ecf120246e7d3e5c9a9ed1db637914bbf4b5702 URL: https://github.com/llvm/llvm-project/commit/1ecf120246e7d3e5c9a9ed1db637914bbf4b5702 DIFF: https://github.com/llvm/llvm-project/commit/1ecf120246e7d3e5c9a9ed1db637914bbf4b5702.diff

[clang] bea5e88 - [clang][Sema] Fix typo in checkBuiltinArgument helper

Author: Alex Bradbury Date: 2022-04-20T14:42:41+01:00 New Revision: bea5e88bcf5908b676da35fb8c64f9f8449ba73b URL: https://github.com/llvm/llvm-project/commit/bea5e88bcf5908b676da35fb8c64f9f8449ba73b DIFF: https://github.com/llvm/llvm-project/commit/bea5e88bcf5908b676da35fb8c64f9f8449ba73b.diff

[clang] 4f40ca5 - [RISCV] Implement support for the Zicbom and Zicboz extensions

Author: Alex Bradbury Date: 2022-06-28T12:43:25+01:00 New Revision: 4f40ca53cefb725aca6564585d0ec4836a79e21a URL: https://github.com/llvm/llvm-project/commit/4f40ca53cefb725aca6564585d0ec4836a79e21a DIFF: https://github.com/llvm/llvm-project/commit/4f40ca53cefb725aca6564585d0ec4836a79e21a.diff

[clang] 7bcfcab - [RISCV] Implement support for the Zicbop extension

Author: Alex Bradbury Date: 2022-06-28T12:43:26+01:00 New Revision: 7bcfcabbd14e9cd51d150a36aee9edf4f4231724 URL: https://github.com/llvm/llvm-project/commit/7bcfcabbd14e9cd51d150a36aee9edf4f4231724 DIFF: https://github.com/llvm/llvm-project/commit/7bcfcabbd14e9cd51d150a36aee9edf4f4231724.diff

[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

asb wrote: This is a user-facing change that definitely needs to be acknowledged in the release notes (clang/docs/ReleaseNotes.rst) I agree with you that it seems more intuitive that a -march=rv32imaf invocation should default to ilp32f just as -march=rv32imafd defaults to ilp32d. I slightly

[llvm] [clang] [RISCV] Remove experimental from Vector Crypto extensions (PR #74213)

asb wrote: I failed to report back in the other review thread about the discussion at the previous RISC-V LLVM sync-up call. I think it's a fair summary to say we concluded was that gating the intrinsics on a flag was a good idea (though not a strict requirement if it was going to slow things

[clang] [llvm] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

asb wrote: I think the conclusion from the LLVM sync-up call was that everyone happy to move in this direction, so please add the release note and we can do a final review. Thanks! https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits maili

[clang] [llvm] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

asb wrote: > > I think the conclusion from the LLVM sync-up call was that everyone happy > > to move in this direction, so please add the release note and we can do a > > final review. Thanks! > > Done, added release note. Thanks! Sorry I wasn't specific about this, but we need a Clang releas

[llvm] [clang] Remove experimental from Vector Crypto extensions (PR #69000)

asb wrote: > Since it's possible that **ISA spec** and **intrinsics spec** are not > synchronized, so the updates add an dummy extension called **zexperimental**, > once `-menable-experimental-extensions` is specified, the feature > `zexperimental` is automatically added. > If `let RequiredFea

[clang] [llvm] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)

https://github.com/asb approved this pull request. I think everyone is happy, so please go ahead and squash+merge. Thanks! https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cg

[clang] [clang] Enable --gcc-install-dir for RISCV baremetal toolchains (PR #71803)

asb wrote: Tagging @MaskRay for a quick check of this too, if he has time. https://github.com/llvm/llvm-project/pull/71803 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)

asb wrote: @dtcxzyw Could you please confirm the status of this core - is it commercially available, an academic test chip, something else? https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https:/

[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)

asb wrote: > > @dtcxzyw Could you please confirm the status of this core - is it > > commercially available, an academic test chip, something else? > > It's maintained by Beijing Institute of Open Source Chip (BOSC), a non-profit > organziation founded by companies and researech institutions.

[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)

asb wrote: > Xiangshan is of great famousness in China and there is already a community in > which many individual developers and organiztions/companies like PLCT, T-Head > have participated. So I think we needn't worry about the maintenance. :-) Thanks for that extra context! https://github.

[lldb] [mlir] [polly] [lld] [libcxx] [flang] [llvm] [clang] [compiler-rt] [openmp] [libc] [WebAssembly] Correctly consider signext/zext arg flags at function declaration (PR #77281)

asb wrote: In case anyone was wondering how this is handled in SelectionDAG, I believe it's covered by CallLoweringInfo ultimately determining if an arg is sext/zext through CallBase::paramHasAttr, which does indeed check both the callsite and the called function (if it's a direct call of cour

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

asb wrote: The RISCVUsage change looks good to me, and it's fantastic that @nemanjai might be able to help push this forward further. I think all the review comments were addressed, so I'd be happy to merge if @topperc is happy his comments were resolved. Though also fine to wait longer if @n

[clang] [llvm] [Clang][RISCV] Move getVScaleRange logic into libLLVMFrontendDriver. NFC (PR #77327)

asb wrote: libLLVMFrontendDriver intuitively seems like a sensible home, though I think we'd be the first to use it in this way. I'm wondering if you considered moving the helper function into RISCVISAInfo? I'm not sure it's _better_ but it doesn't seem like a terrible place for this logic. h

[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)

https://github.com/asb approved this pull request. LGTM, but please add a release note too. https://github.com/llvm/llvm-project/pull/77458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-comm

[clang] Remove experimental from Vector Crypto extensions (PR #69000)

asb wrote: Thanks for the patch, some very quick feedback and I'd highlight the first bullet as the most important, as this is potentially a blocker for graduating these extensions from experimental. * My big concern with this would be the intrinsics - could you please comment on the status o

[clang] [clang] [unittest] Add a test for Generic_GCC::GCCVersion::Parse (PR #69078)

asb wrote: @tbaederr Just came to report the same thing! @mstorsjo This broke builds that use `-DBUILD_SHARED_LIBS=True`. The problem seems to be that the `Generic_GCC` class has the `LLVM_LIBRARY_VISIBILITY` attribute meaning the `clang::driver::toolchains::Generic_GCC::GCCVersion::Parse(llv

[clang] [RISCV] Run mem2reg to simplify Zbc tests (PR #70169)

https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/70169 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Minor improvements/cleanup to target attribute handling. NFC (PR #73851)

https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/73851 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

https://github.com/asb approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove experimental from Vector Crypto extensions (PR #74213)

https://github.com/asb approved this pull request. I was sure I LGTMed this earlier today, but it seems I didn't... https://github.com/llvm/llvm-project/pull/74213 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/m

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

asb wrote: The conclusion from the previous review was this was OK to merge. I think I held it up by not responding to a ping (apologies). I've had another scan through and don't see a problem with merging this and considering it experimental once Craig's review comments are addressed. For th

[clang] [llvm] [RISCV] Add B extension (PR #76893)

asb wrote: Thanks! If someone sets zba_zbb_zbs, should b be inferred? This patch needs an LLVM release note as well, and agreed we should await on a versioning decision. https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cf

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

asb wrote: @nemanjai I'm curious if you have an interest / need to support RVE or not? https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -179,6 +180,11 @@ Assembly Support Supported Fully supported by the compiler. This includes everything in Assembly Support, along with - if relevant - C language intrinsics for the instructions and pattern matching by the compiler to recognize idiomatic patterns which ca

r351540 - [analyzer] Unbreak building of SymbolReaperTest true BUILD_SHARED_LIBS=True

Author: asb Date: Fri Jan 18 02:13:07 2019 New Revision: 351540 URL: http://llvm.org/viewvc/llvm-project?rev=351540&view=rev Log: [analyzer] Unbreak building of SymbolReaperTest true BUILD_SHARED_LIBS=True Extra dependencies need to be listed for StaticAnalysisTests in order for linking to succee

Re: r347720 - [RISCV] Mark unit tests as "requires: riscv-registered-target"

On Tue, 27 Nov 2018 at 22:56, Mandeep Singh Grang via cfe-commits wrote: > > Author: mgrang > Date: Tue Nov 27 14:53:57 2018 > New Revision: 347720 > > URL: http://llvm.org/viewvc/llvm-project?rev=347720&view=rev > Log: > [RISCV] Mark unit tests as "requires: riscv-registered-target" > > Some of t

Re: r347720 - [RISCV] Mark unit tests as "requires: riscv-registered-target"

On Thu, 29 Nov 2018 at 09:44, Alex Bradbury wrote: > > On Tue, 27 Nov 2018 at 22:56, Mandeep Singh Grang via cfe-commits > wrote: > > > > Author: mgrang > > Date: Tue Nov 27 14:53:57 2018 > > New Revision: 347720 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=347720&view=rev > > Log: > > [R

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

asb wrote: CC @petrhosek too who I know [hopes to merge the RISCVToolChain and BareMetal toolchains](https://discourse.llvm.org/t/merging-riscvtoolchain-and-baremetal-toolchains/75524). Matching the GCC behaviour seems sensible to me, and I'm hopeful that the planned future refactoring will av

[clang] [clang] Define SwiftInfo for RISCVTargetCodeGenInfo (PR #82152)

asb wrote: Yes, please add a trivial test if at all possible. https://github.com/llvm/llvm-project/pull/82152 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

asb wrote: > > I don't know if we need S-mode profile CPUs. > > I lean towards not supporting them since the S extensions don't do anything > in the compiler except preprocessor defines and ELF attributes, but maybe we > should put it on the agenda for the sync meeting this week. My initial f

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

asb wrote: We discussed this on the sync-up call and @preames very rightly pointed out that we should take a step back here...from a user perspective, what does specifying a profile via `-mcpu` provide that specifying it via `-march` doesn't? We weren't able to answer that in the call, but per

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

asb wrote: > In my view, the builtin solution is superior from a usability perspective. I agree, I think Sam's previous work on this stopped due to changing priorities not because there was any real pushback. https://github.com/llvm/llvm-project/pull/85091 _

[clang] [llvm] [RISCV] Add B extension (PR #76893)

asb wrote: > It passed public review[1] and merged into riscv-isa-manual[2], so I think > it's time to mark it as 1.0 and moving forward :) > > [1] > https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/KetVUCQkfK4/m/Y3Dbd2pvAAAJ?utm_medium=email&utm_source=footer > [2] > [riscv/riscv-is

[clang] [llvm] [RISCV] Graduate Zicond to non-experimental (PR #79811)

https://github.com/asb created https://github.com/llvm/llvm-project/pull/79811 The Zicond extension was ratified in the last few months, with no changes that affect the LLVM implementation. Although there's surely more tuning that could be done about when to select Zicond or not, there are no k

[clang] [llvm] [RISCV] Graduate Zicond to non-experimental (PR #79811)

https://github.com/asb updated https://github.com/llvm/llvm-project/pull/79811 >From cf5c3432f66b36db0b8283a967b24686433cdf63 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Sun, 28 Jan 2024 08:50:35 + Subject: [PATCH 1/2] [RISCV] Graduate Zicond to non-experimental The Zicond extension

[llvm] [clang] [RISCV] Graduate Zicond to non-experimental (PR #79811)

asb wrote: > Should we backport this to llvm 18? I'd be inclined to do so if there are no objections. https://github.com/llvm/llvm-project/pull/79811 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listin

[clang] [llvm] [RISCV] Graduate Zicond to non-experimental (PR #79811)

https://github.com/asb closed https://github.com/llvm/llvm-project/pull/79811 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Ssqosid support to -march. (PR #80747)

https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/80747 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add -march string as Module metadata in IR. (PR #80760)

asb wrote: I agree that finding a generic cross-target solution to this problem is attractive...but I worry it will be hard and slow to proceed. It's possible the previous discussions just lacked someone following up with concrete patches, but I do worry we'd end up stuck in limbo vs starting

[clang] [llvm] [RISCV] Add Zic64b, Ziccamoa, Ziccif, Zicclsm, Ziccrse, and Za64rs to sifive-p450. (PR #79030)

https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/79030 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)

@@ -1307,6 +1309,13 @@ // CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}} // Experimental extensions +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zaamo0p1 -x c -E -dM %s \ asb wrote: I'm confused how/if this is actually

[llvm] [clang] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #77424)

asb wrote: There should be a release note for this as well as the RISCVUsage update. I have concerns that the codegen part of this isn't correct. Specifically, the [requirement](https://llvm.org/docs/Atomics.html#atomics-and-codegen) that "One very important property of the atomic operations i

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

https://github.com/asb approved this pull request. LGTM. Thanks for your persistence on this! https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-co

[llvm] [clang] [RISCV] Bump Zfbfmin, Zvfbfmin, and Zvfbfwma to 1.0. (PR #78021)

https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/78021 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)

asb wrote: Just to check, can someone confirm if gcc is now handling ISA strings in this way too? I do think this is the right direction to go but haven't done a detailed code review of this approach yet. https://github.com/llvm/llvm-project/pull/78120 _

[clang] [llvm] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #77424)

asb wrote: CC @jyknight who can hopefully confirm if my interpretation is correct. Based on your comment on #77814, perhaps the expectation is that libatomic would have a lock-free implementation for any __sync calls used up to the max atomic width (e.g. lr/sc based if there's no AMO instructi

[clang] [llvm] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #77424)

asb wrote: Thanks James, that matches what I'd understood. Just one comment on this though: > If Zaamo is present, but neither Zalrsc nor Zacas are present, I think > there's no way to implement a cmpxchg operation. This means lock-free atomics > cannot be supported, so it should `setMaxAtomic

[llvm] [clang] [RISCV] Add experimental support of Zaamo and Zalrsc (PR #77424)

asb wrote: > However, I must say, I cannot understand why this is even a thing that anyone > would want. Why would anyone design a single-processor RISCV system that > doesn't implement LR/SC? If you don't have the issue of coherent memory > across multiple CPUs, LR/SC is utterly trivial to im

[clang] [RISCV] Re-order riscv-target-features.c to put non-experimental extensions together. (PR #78675)

https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/78675 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add generic CPUs for profiles (PR #84877)

asb wrote: We discussed again in the sync-up call to try to move this forwards and per a discussion with @topperc and @preames were wondering if relying on -mattr and a corresponding feature for the profile might be the better approach after all. * There's not a lot of instances of this, but I

[clang] [llvm] [llvm][RISCV] Improve error message for invalid extension letters (PR #90468)

https://github.com/asb approved this pull request. LGTM, thanks. https://github.com/llvm/llvm-project/pull/90468 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Refactor profile selection in RISCVISAInfo::parseArchString. (PR #90700)

https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/90700 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add smstateen extension (PR #90818)

https://github.com/asb approved this pull request. Release note and RISCVUsage and it LGTM. https://github.com/llvm/llvm-project/pull/90818 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-comm

[clang] [llvm] [RISCV] Gate unratified profiles behind -menable-experimental-extensions (PR #92167)

https://github.com/asb created https://github.com/llvm/llvm-project/pull/92167 As discussed in the last sync-up call, because these profiles are not yet finalised they shouldn't be exposed to users unless they opt-in to them (much like experimental extensions). We may later want to add a more s

[clang] [llvm] [RISCV] Gate unratified profiles behind -menable-experimental-extensions (PR #92167)

https://github.com/asb updated https://github.com/llvm/llvm-project/pull/92167 >From 5159fce9b2cca245335e124f7f0cd2149cdbcb2a Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Tue, 14 May 2024 20:45:41 +0100 Subject: [PATCH] [RISCV] Gate unratified profiles behind -menable-experimental-extensi

[clang] [llvm] [RISCV] Gate unratified profiles behind -menable-experimental-extensions (PR #92167)

https://github.com/asb closed https://github.com/llvm/llvm-project/pull/92167 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Gate unratified profiles behind -menable-experimental-extensions (PR #92167)

asb wrote: Thank you for the reviews - I've gone ahead and merged. One thing from the added tests that's worth highlighting perhaps is `RejectsProfilesWithAdditionalExtensionsGivenAlreadyInProfile` which documents that currently if you specify an extension that's already part of the profile t

[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)

@@ -0,0 +1,1664 @@ +//=- AArch64SchedOryon.td - Nuvia Inc Oryon CPU 001 ---*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.

[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)

https://github.com/asb edited https://github.com/llvm/llvm-project/pull/91022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)

https://github.com/asb edited https://github.com/llvm/llvm-project/pull/91022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64] Add support for Qualcomm Oryon processor (PR #91022)

@@ -0,0 +1,1664 @@ +//=- AArch64SchedOryon.td - Nuvia Inc Oryon CPU 001 ---*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.

[clang] [llvm] [RISCV] Add riscv_atomic.h and Zawrs/Zalrsc builtins (PR #94578)

asb wrote: My understanding from the sync-up call just now is you're planning to drop lr/sc intrinsics due to the concerns listed in this thread (which I share), but will keep pushing the zawrs intrinsics. https://github.com/llvm/llvm-project/pull/94578

[clang] d17de54 - [clang][RISCV][test] Add test that shows incorrect ABI lowering

Author: Alex Bradbury Date: 2022-08-11T18:51:37+01:00 New Revision: d17de5479c6234f9e37fb4deca9e537bf8d3932e URL: https://github.com/llvm/llvm-project/commit/d17de5479c6234f9e37fb4deca9e537bf8d3932e DIFF: https://github.com/llvm/llvm-project/commit/d17de5479c6234f9e37fb4deca9e537bf8d3932e.diff

[clang] bc53832 - [clang][RISCV] Fix incorrect ABI lowering for inherited structs under hard-float ABIs

Author: Alex Bradbury Date: 2022-08-19T20:31:06+01:00 New Revision: bc538320809fb52af12ec0366118c82201af4f40 URL: https://github.com/llvm/llvm-project/commit/bc538320809fb52af12ec0366118c82201af4f40 DIFF: https://github.com/llvm/llvm-project/commit/bc538320809fb52af12ec0366118c82201af4f40.diff

[clang] [RISCV] Update Zfa extension version to 1.0 (PR #67964)

https://github.com/asb created https://github.com/llvm/llvm-project/pull/67964 The Zfa specification was recently ratified . This commit bumps the version to 1.0, but leaves it as an experimental extension (to be done in a follow

[clang] 17a58b3 - [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

Author: Alex Bradbury Date: 2023-07-24T10:24:34+01:00 New Revision: 17a58b3ca7ec18585e9ea8ed8b39d72fe36fb6cb URL: https://github.com/llvm/llvm-project/commit/17a58b3ca7ec18585e9ea8ed8b39d72fe36fb6cb DIFF: https://github.com/llvm/llvm-project/commit/17a58b3ca7ec18585e9ea8ed8b39d72fe36fb6cb.diff

[clang] 569e99a - [clang][docs] Attempt to fix warning when building ReleaseNotes

Author: Alex Bradbury Date: 2023-07-24T10:36:42+01:00 New Revision: 569e99a471f618b7fdf045d5e96f21d3e3a7f898 URL: https://github.com/llvm/llvm-project/commit/569e99a471f618b7fdf045d5e96f21d3e3a7f898 DIFF: https://github.com/llvm/llvm-project/commit/569e99a471f618b7fdf045d5e96f21d3e3a7f898.diff

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