[clang] [Clang][SPIRV][AMDGPU] Override `supportsLibCall` for AMDGCNSPIRV (PR #143814)

https://github.com/AlexVlx commented: > Well, I'm not sure if my review is gating here, if "AMDGPU does not support > any libcalls at the moment" - it is what it is, no objections from my side. Since I am modifying the shared CodeGenInfo bit, it made sense to ask:) Also, I wasn't entirely cer

[clang] [Clang][SPIRV][AMDGPU] Override `supportsLibCall` for AMDGCNSPIRV (PR #143814)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/143814 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][SPIRV][AMDGPU] Override `supportsLibCall` for AMDGCNSPIRV (PR #143814)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/143814 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,157 @@ +//===- AMDGPUExpandFeaturePredicates.cpp - Feature Predicate Expander Pass ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,157 @@ +//===- AMDGPUExpandFeaturePredicates.cpp - Feature Predicate Expander Pass ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,157 @@ +//===- AMDGPUExpandFeaturePredicates.cpp - Feature Predicate Expander Pass ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -9102,6 +9102,15 @@ bool InitializationSequence::Diagnose(Sema &S, case FK_ConversionFailed: { QualType FromType = OnlyArg->getType(); +// __amdgpu_feature_predicate_t can be explicitly cast to the logical op +// type, although this is almost always an error a

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > I'm generally very unhappy about any kind of functionality that can cause > compilation failures either because the optimizer did not optimize enough > (including at O0) or because it optimized too much (producing code patterns > that are no longer recognized as trivially dead

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,157 @@ +//===- AMDGPUExpandFeaturePredicates.cpp - Feature Predicate Expander Pass ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,157 @@ +//===- AMDGPUExpandFeaturePredicates.cpp - Feature Predicate Expander Pass ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [HIP] Emit the CUID value in the module with the new driver (PR #144570)

https://github.com/AlexVlx approved this pull request. LGTM, thanks. https://github.com/llvm/llvm-project/pull/144570 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -9102,6 +9102,15 @@ bool InitializationSequence::Diagnose(Sema &S, case FK_ConversionFailed: { QualType FromType = OnlyArg->getType(); +// __amdgpu_feature_predicate_t can be explicitly cast to the logical op +// type, although this is almost always an error a

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -9102,6 +9102,15 @@ bool InitializationSequence::Diagnose(Sema &S, case FK_ConversionFailed: { QualType FromType = OnlyArg->getType(); +// __amdgpu_feature_predicate_t can be explicitly cast to the logical op +// type, although this is almost always an error a

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -9102,6 +9102,15 @@ bool InitializationSequence::Diagnose(Sema &S, case FK_ConversionFailed: { QualType FromType = OnlyArg->getType(); +// __amdgpu_feature_predicate_t can be explicitly cast to the logical op +// type, although this is almost always an error a

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -9102,6 +9102,15 @@ bool InitializationSequence::Diagnose(Sema &S, case FK_ConversionFailed: { QualType FromType = OnlyArg->getType(); +// __amdgpu_feature_predicate_t can be explicitly cast to the logical op +// type, although this is almost always an error a

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: Gentle ping. https://github.com/llvm/llvm-project/pull/134016 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][SPIRV][AMDGPU] Override `supportsLibCall` for AMDGCNSPIRV (PR #143814)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/143814 >From a976da9d6033a252fab75de216fe6580d6e3e6ff Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Thu, 12 Jun 2025 00:47:43 +0100 Subject: [PATCH 1/2] Override `SPIRVTargetCodeGenInfo::supportsLibCall()` in order

[clang] [Clang][SPIRV][AMDGPU] Override `supportsLibCall` for AMDGCNSPIRV (PR #143814)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/143814 >From a976da9d6033a252fab75de216fe6580d6e3e6ff Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Thu, 12 Jun 2025 00:47:43 +0100 Subject: [PATCH 1/2] Override `SPIRVTargetCodeGenInfo::supportsLibCall()` in order

[clang] [Clang][SPIRV][AMDGPU] Override `supportsLibCall` for AMDGCNSPIRV (PR #143814)

https://github.com/AlexVlx commented: #143431 is related to this, but it proposes a more pervasive change, which would require further discussion and clarification around what the SPIR-V BE wants to do / support in term of libcalls. https://github.com/llvm/llvm-project/pull/143814

[clang] [Clang][SPIRV][AMDGPU] Override `supportsLibCall` for AMDGCNSPIRV (PR #143814)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/143814 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][SPIRV][AMDGPU] Override `supportsLibCall` for AMDGCNSPIRV (PR #143814)

https://github.com/AlexVlx created https://github.com/llvm/llvm-project/pull/143814 The `supportsLibCall` predicate is used to select whether some math builtins get expanded in the FE or they get lowered into libcalls. The default implementation unconditionally returns true, which is problemat

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,21 @@ +// REQUIRES: amdgpu-registered-target +// REQUIRES: spirv-registered-target +// RUN: %clang_cc1 -fsyntax-only -verify -triple amdgcn -Wno-unused-value %s +// RUN: %clang_cc1 -fsyntax-only -verify -triple spirv64-amd-amdhsa -Wno-unused-value %s +// RUN: %clang_cc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: Gentle ping. https://github.com/llvm/llvm-project/pull/134016 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/134016 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx commented: > First, please take a look at the LLVM coding standard re the use of 'auto'. > > Second: The use of a special type for these builtins is a little novel > (though I see the predicate type already exists?), but I guess I'm ok with > it. I have some concern

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4966,6 +4966,89 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __buil

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -29,6 +29,8 @@ MODULE_PASS("amdgpu-printf-runtime-binding", AMDGPUPrintfRuntimeBindingPass()) MODULE_PASS("amdgpu-remove-incompatible-functions", AMDGPURemoveIncompatibleFunctionsPass(*this)) MODULE_PASS("amdgpu-sw-lower-lds", AMDGPUSwLowerLDSPass(*this)) MODULE_PASS("amdg

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -13338,4 +13338,23 @@ def err_acc_device_type_multiple_archs // AMDGCN builtins diagnostics def err_amdgcn_load_lds_size_invalid_value : Error<"invalid size value">; def note_amdgcn_load_lds_size_valid_value : Note<"size must be %select{1, 2, or 4|1, 2, 4, 12 or 16}0">; +de

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: Gentle ping. https://github.com/llvm/llvm-project/pull/134016 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [HIP] change default offload archs (PR #139281)

AlexVlx wrote: I think that in general we also need to decide on what happens when you pick an amdgcn— triple. IMHO for that case we should probably error out if no mcpu is provided, since there’s no reasonable default, except for “all”, but that would be incredibly disruptive. https://github

[clang] [HIP] change default offload archs (PR #139281)

AlexVlx wrote: > > > The main obstacle of letting clang emit error when `--offload-arch` is > > > not specified is HIP apps using hipcc as CMAKE_CXX_COMPILER. hipcc adds > > > -xhip by default for .cpp programs. This is a known and long existing > > > issue. > > > Another option is to have mul

[clang] [HIP] change default offload archs (PR #139281)

AlexVlx wrote: > The main obstacle of letting clang emit error when `--offload-arch` is not > specified is HIP apps using hipcc as CMAKE_CXX_COMPILER. hipcc adds -xhip by > default for .cpp programs. This is a known and long existing issue. > > Another option is to have multiple `--offload-arc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-s

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: @erichkeane @AaronBallman if, when you have time, you could please indicate if the new direction is at least generally aligned with what you had in mind, it'd be appreciated! https://github.com/llvm/llvm-project/pull/134016 ___ cfe-com

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-s

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/134016 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx commented: > A side question, is it legal to use the builtin in unstructured control flow, > like here: https://godbolt.org/z/no7Kzv19r ? Note, if the answer is "no", > then enforcing the builtin to initialize something would (probably) > automatically prevent this c

[clang] [llvm] [HIP][HIPSTDPAR] Re-work allocation interposition for `hipstdpar` (PR #138790)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/138790 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HIP][HIPSTDPAR] Re-work allocation interposition for `hipstdpar` (PR #138790)

https://github.com/AlexVlx created https://github.com/llvm/llvm-project/pull/138790 The allocation interposition mode had a number of issues, which are primarily addressed in the library component via . However, it is necessary to interpose some add

[clang] [llvm] [HIP][HIPSTDPAR] Re-work allocation interposition for `hipstdpar` (PR #138790)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/138790 >From 865ff3dff1833607f0d546ab0ebd95b98a8ed71b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 7 May 2025 01:25:17 +0100 Subject: [PATCH 1/2] Re-work allocation interposition for `hipstdpar`. --- clang/do

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-s

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-s

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix AS of globals and set the default AS to 4 (PR #135251)

@@ -1217,11 +1217,13 @@ void CGOpenMPRuntimeGPU::emitParallelCall(CodeGenFunction &CGF, CGBuilderTy &Bld = CGF.Builder; llvm::Value *NumThreadsVal = NumThreads; llvm::Function *WFn = WrapperFunctionsMap[OutlinedFn]; +llvm::FunctionCallee RuntimeFn = OMPBuilder.

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix AS of globals and set the default AS to 4 (PR #135251)

AlexVlx wrote: Overall this seems a bit AS cast heavy in the OMP parts, I wonder if we have a chance to figure out if we cannot just emit things in the right ASes from the get-go? This is the path we took when cleaning up some of this stuff in Clang for C/C++, and whilst it was definitely more

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix AS of globals and set the default AS to 4 (PR #135251)

@@ -1217,11 +1217,13 @@ void CGOpenMPRuntimeGPU::emitParallelCall(CodeGenFunction &CGF, CGBuilderTy &Bld = CGF.Builder; llvm::Value *NumThreadsVal = NumThreads; llvm::Function *WFn = WrapperFunctionsMap[OutlinedFn]; +llvm::FunctionCallee RuntimeFn = OMPBuilder.

[clang] [clang][SPIR-V] Addrspace of opencl_global should always be 1 (PR #136753)

https://github.com/AlexVlx approved this pull request. LGTM, thanks! FWIW, perhaps it'd be worthwhile (as a follow-up, not here) to simply make the DefIsGen AS map correct/valid, and replace the dummy bits? https://github.com/llvm/llvm-project/pull/136753 ___

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > > You could default the warning to an error to make it more visible to the > user. Not certain if that's a bad idea or not though. > Possibly. I had to drop this for a bit so circling around again, so apologies for the late reply. In the meanwhile, @epilk pointed out somethi

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

AlexVlx wrote: > LLVM Buildbot has detected a new failure on builder > `llvm-clang-x86_64-sie-ubuntu-fast` running on `sie-linux-worker` while > building `clang,llvm` at step 6 "test-build-unified-tree-check-all". > > Full details are available at: > https://lab.llvm.org/buildbot/#/builders/1

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 01/11] Add the functional identity and feature queries. --- clang/d

[clang] [llvm] [NFC] Fix bot breakage introduced by #134753 (PR #135697)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/135697 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NFC] Fix bot breakage introduced by #134753 (PR #135697)

https://github.com/AlexVlx created https://github.com/llvm/llvm-project/pull/135697 This test needs the amdgpu target, and its absence wreaked havoc with some of the bots, therefore we now require it. >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Dat

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/134753 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/8] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/7] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/7] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -0,0 +1,21 @@ +// Test that the accelerator code selection pass only gets invoked after linking + +// Ensure Pass HipStdParAcceleratorCodeSelectionPass is not invoked in PreLink. +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -mllvm -amdgpu-enable-hipstdpar -flto -emit-llvm-bc

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -0,0 +1,21 @@ +// Test that the accelerator code selection pass only gets invoked after linking + +// Ensure Pass HipStdParAcceleratorCodeSelectionPass is not invoked in PreLink. +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -mllvm -amdgpu-enable-hipstdpar -flto -emit-llvm-bc

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -0,0 +1,11 @@ +// Check that if we are compiling with fgpu-rdc amdgpu-enable-hipstdpar is not +// passed to CC1, to avoid eager, per TU, removal of potentially accessible +// functions. + +// RUN: %clang -### --hipstdpar --offload-arch=gfx906 %s -nogpulib -nogpuinc \ +// RUN:

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/6] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/5] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -0,0 +1,11 @@ +// Check that if we are compiling with fgpu-rdc amdgpu-enable-hipstdpar is not +// passed to CC1, to avoid eager, per TU, removal of potentially accessible +// functions. + +// RUN: %clang -### --hipstdpar --offload-arch=gfx906 %s -nogpulib -nogpuinc \ +// RUN:

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -883,6 +883,12 @@ void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { PB.registerFullLinkTimeOptimizationLastEPCallback( [this](ModulePassManager &PM, OptimizationLevel Level) { +// When we are using -fgpu-rdc, we can onky run accelera

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/4] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/3] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -37,8 +37,8 @@ static const unsigned SPIRDefIsPrivMap[] = { 0, // cuda_device 0, // cuda_constant 0, // cuda_shared -// SYCL address space values for this map are dummy -0, // sycl_global +// Most SYCL address space values for this map are dummy -

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -5384,6 +5384,11 @@ LangAS CodeGenModule::GetGlobalVarAddressSpace(const VarDecl *D) { LangAS AS; if (OpenMPRuntime->hasAllocateAttributeForGlobalVar(D, AS)) return AS; +if (LangOpts.OpenMPIsTargetDevice && getTriple().isSPIRV()) AlexVlx w

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -5384,6 +5384,11 @@ LangAS CodeGenModule::GetGlobalVarAddressSpace(const VarDecl *D) { LangAS AS; if (OpenMPRuntime->hasAllocateAttributeForGlobalVar(D, AS)) return AS; +if (LangOpts.OpenMPIsTargetDevice && getTriple().isSPIRV()) AlexVlx w

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -37,8 +37,8 @@ static const unsigned SPIRDefIsPrivMap[] = { 0, // cuda_device 0, // cuda_constant 0, // cuda_shared -// SYCL address space values for this map are dummy -0, // sycl_global +// Most SYCL address space values for this map are dummy -

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

https://github.com/AlexVlx approved this pull request. LGTM, thanks! https://github.com/llvm/llvm-project/pull/134399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx commented: > Needs test Done. https://github.com/llvm/llvm-project/pull/134753 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/3] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/134753 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -37,8 +37,8 @@ static const unsigned SPIRDefIsPrivMap[] = { 0, // cuda_device 0, // cuda_constant 0, // cuda_shared -// SYCL address space values for this map are dummy -0, // sycl_global +// Most SYCL address space values for this map are dummy -

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > > This change adds two semi-magical builtins for AMDGPU: > > ``` > > * `__builtin_amdgcn_processor_is`, which is similar in observable behaviour > > with `__builtin_cpu_is`, except that it is never "evaluated" at run time; > > > > * `__builtin_amdgcn_is_invocable`, which is beh

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -15576,6 +15609,38 @@ static bool isOverflowingIntegerType(ASTContext &Ctx, QualType T) { return Ctx.getIntWidth(T) >= Ctx.getIntWidth(Ctx.IntTy); } +static Expr *ExpandAMDGPUPredicateBI(ASTContext &Ctx, CallExpr *CE) { + if (!CE->getBuiltinCallee()) +return CXXBool

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,64 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCN-GFX900 %s +// RUN: %cla

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/7] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -5384,6 +5384,11 @@ LangAS CodeGenModule::GetGlobalVarAddressSpace(const VarDecl *D) { LangAS AS; if (OpenMPRuntime->hasAllocateAttributeForGlobalVar(D, AS)) return AS; +if (LangOpts.OpenMPIsTargetDevice && getTriple().isSPIRV()) AlexVlx w

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -5402,6 +5407,10 @@ LangAS CodeGenModule::GetGlobalConstantAddressSpace() const { // UniformConstant storage class is not viable as pointers to it may not be // casted to Generic pointers which are used to model HIP's "flat" pointers. return LangAS::cuda_device

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > So in short: what you're trying to prevent is "this was stored in a variable, > then checked later when we are no longer on the device, thus the answer is > different". Not quite, although that is definitely an interesting consideration. What I am trying to address here is t

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > > as a must have, it allows featureful AMDGCN flavoured SPIR-V to be > > produced, where target specific capability is guarded and chosen or > > discarded when finalising compilation for a concrete target. > > I understand the reasoning behind providing such mechanisms to guar

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 01/10] Add the functional identity and feature queries. --- clang/d

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 01/11] Add the functional identity and feature queries. --- clang/d

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -585,6 +597,23 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, llvm::Value *Env = EmitScalarExpr(E->getArg(0)); return Builder.CreateCall(F, {Env}); } + case AMDGPU::BI__builtin_amdgcn_processor_is: { +assert(CGM.getTriple().isSPIRV() &&

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,64 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCN-GFX900 %s +// RUN: %cla

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/9] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/8] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -284,6 +284,18 @@ void CodeGenFunction::AddAMDGPUFenceAddressSpaceMMRA(llvm::Instruction *Inst, Inst->setMetadata(LLVMContext::MD_mmra, MMRAMetadata::getMD(Ctx, MMRAs)); } +static Value *GetOrInsertAMDGPUPredicate(CodeGenFunction &CGF, Twine Name) { + auto PTy = Integer

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -15576,6 +15609,38 @@ static bool isOverflowingIntegerType(ASTContext &Ctx, QualType T) { return Ctx.getIntWidth(T) >= Ctx.getIntWidth(Ctx.IntTy); } +static Expr *ExpandAMDGPUPredicateBI(ASTContext &Ctx, CallExpr *CE) { + if (!CE->getBuiltinCallee()) +return CXXBool

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -585,6 +597,23 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, llvm::Value *Env = EmitScalarExpr(E->getArg(0)); return Builder.CreateCall(F, {Env}); } + case AMDGPU::BI__builtin_amdgcn_processor_is: { +assert(CGM.getTriple().isSPIRV() &&

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/5] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/6] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/4] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > This is worth a release note item. Indeed! I botched moving the changes from my internal scratchpad, and the rel notes got lost; fixing. https://github.com/llvm/llvm-project/pull/134016 ___ cfe-commits mailing list cfe-commits@lists.

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,64 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCN-GFX900 %s +// RUN: %cla

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