https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/94318
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4vtomat wrote:
> Could you give few more word on the description to mention we missed that in
> the vector crpyto intrinsic proposal, and it's fixing but rather than
> incompatible/breaking change for the intrinsic API?
Updated description. We are missing `vcpop.v` in the rvv_intrinsic_doc,
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/94318
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4vtomat wrote:
> FYI, the example code you shown doesn't compile anymore:
> https://godbolt.org/z/ooTWEGejf
>
> This feature is quite important, without it we can't compile in RVV by
> default in a lot of libraries, e.g. simdutf, flac, ...
I guess it should be
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https://github.com/llvm/llvm-project/pull/91556
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>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/4] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/91556
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/3] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified
@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
4vtomat wrote:
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/92644
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/92644
The NumVectors other than 1 is handled by the code above.
>From 4dbcf6e577d5f1aea0cde72e3a5a7fd73620b2d9 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 18 May 2024 03:07:43 -0700
Subject: [PATCH] [RISCV]
4vtomat wrote:
> > > Need to update RISCVUsage.rst and ReleaseNotes.rst
> >
> >
> > Is it going to be cherry-picked to release branch?
>
> No. We just try to update the ReleaseNotes proactively for LLVM 19.
Got it!
https://github.com/llvm/llvm-project/pull/91556
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/91556
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/2] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified
4vtomat wrote:
> Need to update RISCVUsage.rst and ReleaseNotes.rst
Is it going to be cherry-picked to release branch?
https://github.com/llvm/llvm-project/pull/91556
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https://github.com/llvm/llvm-project/pull/91556
The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May
https://github.com/4vtomat approved this pull request.
LGTM～
https://github.com/llvm/llvm-project/pull/90879
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4vtomat wrote:
Ping.
https://github.com/llvm/llvm-project/pull/89883
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https://github.com/llvm/llvm-project/pull/89867
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>From 671bebcb9ad76aa3b43dabada3ab7a75d6934d73 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH 1/2] [Clang][RISCV] Handle RVV tuple types correctly as
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/89883
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/89883
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Get pass validation check for homogeneous scalable
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/89867
>From 4db9d00610f110a163a1b7d5b168461f6a91f4ed Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 23 Apr 2024 20:42:33 -0700
Subject: [PATCH] [clang][RISCV] Remove LMUL=8 scalar input for some vector
crypto
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/89867
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/89867
Since the minimum requirement is EEW=32, it's impossible that EGW=128
needs LMUL=8.
>From 1ed74c3732194512da7eee2e16bc252269f0e6ef Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 23 Apr 2024 20:42:33
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/89354
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4vtomat wrote:
Oh, I forgot to remove them. Or do you think they should be moved to bfloat
folder to make them consistent?
https://github.com/llvm/llvm-project/pull/89354
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https://github.com/llvm/llvm-project/pull/89241
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/89241
Since `vcreate` doesn't support overload, we can remove it.
>From a29cda00de03552529b510eda427804f822278e6 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 18 Apr 2024 07:29:42 -0700
Subject: [PATCH]
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/83674
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4vtomat wrote:
Rebase
https://github.com/llvm/llvm-project/pull/83674
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https://github.com/llvm/llvm-project/pull/83674
>From 10ab0fa16e62e44b8d04b372f20b95018f065048 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/77560
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>From 08371002a08d8958cd23eecb5ff3c5f2f2661c0e Mon Sep 17 00:00:00 2001
From: 4vtomat
Date: Wed, 22 Mar 2023 22:58:35 -0700
Subject: [PATCH] [RISCV] RISCV vector calling convention (1/2)
This is the vector
4vtomat wrote:
Rebase and squash
https://github.com/llvm/llvm-project/pull/77560
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@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+
@@ -36,6 +36,11 @@ struct RISCVSupportedExtension {
}
};
+struct RISCVProfile {
4vtomat wrote:
Very minor too, if you use std::pair, could you add the comments describing
what the fields represent?
https://github.com/llvm/llvm-project/pull/76357
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/83674
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@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const
@@ -3439,6 +3439,8 @@ StringRef FunctionType::getNameForCallConv(CallingConv
CC) {
case CC_PreserveAll: return "preserve_all";
case CC_M68kRTD: return "m68k_rtd";
case CC_PreserveNone: return "preserve_none";
+ case CC_RISCVVectorCall:
4vtomat wrote:
4vtomat wrote:
Rebase.
https://github.com/llvm/llvm-project/pull/83674
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https://github.com/llvm/llvm-project/pull/83674
>From faab3d0d9163e99185fb6a2d3efd21549ed33e00 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/83989
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4vtomat wrote:
> perhaps the llvm libSupport prats of this change should be unit tested in
> LLVM, rather than only tested indirectly in clang?
Good point, thanks!
I've added for unites.
https://github.com/llvm/llvm-project/pull/83989
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https://github.com/llvm/llvm-project/pull/83989
>From 764c861931fd8013df5b144c2d789614bc952126 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 5 Mar 2024 02:28:10 -0800
Subject: [PATCH 1/2] [RISCV] Improve error message when the extension is not
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/83553
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83989
If the "march" has some extension with version that is not supported, it
returns the error message like: "error: invalid arch name 'some_arch',
unsupported version number 2.0 for extension 'some_arch'", which is
4vtomat wrote:
Move the test cases to existing files.
https://github.com/llvm/llvm-project/pull/83674
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83674
>From f14c54cb7c3c31e84a78ddf33b932c4c74e20365 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
4vtomat wrote:
Updated!
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -S -verify %s
+
+// REQUIRES: riscv-registered-target
+#include
+
+void test_builtin() {
+ __riscv_vsetvl_e8m8(1); // expected-error
https://github.com/4vtomat edited
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https://github.com/llvm/llvm-project/pull/83674
>From f14c54cb7c3c31e84a78ddf33b932c4c74e20365 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/2] [clang][RISCV] Enable RVV with function attribute
4vtomat wrote:
> I tried compiling it and then got two warnings.
>
> ```
> llvm-project/clang/lib/CodeGen/CGDebugInfo.cpp:1408:11: warning: enumeration
> value 'CC_RISCVVectorCall' not handled in switch [-Wswitch]
> 1408 | switch (CC) {
> | ^~
> 1 warning generated.
>
4vtomat wrote:
Related request: https://github.com/riscv-non-isa/riscv-c-api-doc/issues/69
https://github.com/llvm/llvm-project/pull/83674
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https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83674
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
4vtomat wrote:
Maybe we can modify the current test case, it would get the error message
"RISC-V type 'vfloat64m1_t' ... requires the 'zve64x' extension", but should be
'zve64d' instead.
https://github.com/llvm/llvm-project/pull/83553
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https://github.com/llvm/llvm-project/pull/83553
>From 8ad3a883d29155dc26c79abdd57ea0f72d046dfc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 00:40:21 -0800
Subject: [PATCH 1/3] [clang][RISCV] Reorder sema check for RVV type
Currently using
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83553
>From 8ad3a883d29155dc26c79abdd57ea0f72d046dfc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 00:40:21 -0800
Subject: [PATCH 1/2] [clang][RISCV] Reorder sema check for RVV type
Currently using
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83553
Currently using the command `clang -cc1 -triple riscv64` to compile the
code below:
```
#include
void foo() {
vfloat64m1_t f64m1;
}
```
would get the error message "RISC-V type 'vfloat64m1_t' ... requires the
4vtomat wrote:
ping
https://github.com/llvm/llvm-project/pull/77560
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4vtomat wrote:
Rebase
https://github.com/llvm/llvm-project/pull/77560
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4vtomat wrote:
The latest fixup commit add [[riscv::riscv_vector]] supports for C23 and C++11.
https://github.com/llvm/llvm-project/pull/77560
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https://github.com/llvm/llvm-project/pull/79615
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@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL =
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@@ -1730,12 +1730,26 @@ let ManualCodegen = [{
defm vfwnmacc : RVVFloatingWidenTerBuiltinSetRoundingMode;
defm vfwmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
defm vfwnmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
+
+// Vector BF16 widening
@@ -0,0 +1,479 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN: -target-feature +zvfh
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL =
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/77487
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>From d52f1e4652f7791413c61cfb075755a46fca8cfa Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 7 Jan 2024 18:10:59 -0800
Subject: [PATCH 1/3] [RISCV][clang] Optimize memory usage of intrinsic lookup
table
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/79407
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https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/79467
>From 6f16a5b2807e1cab5edae90f92cf0145474f4f23 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 25 Jan 2024 08:13:31 -0800
Subject: [PATCH] [RISCV] Add missing dependency check for Zvkb
---
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/79467
>From d451e89a2bf650d3af638a2d22582135ad53cc27 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 25 Jan 2024 08:13:31 -0800
Subject: [PATCH] [RISCV] Add missing dependency check for Zvkb
---
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77487
>From 84ea759c43d8e9cb450d95d00fd802be622153a2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 7 Jan 2024 18:10:59 -0800
Subject: [PATCH 1/3] [RISCV][clang] Optimize memory usage of intrinsic lookup
table
@@ -464,7 +466,8 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult ,
IdentifierInfo *II,
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/79467
None
>From 61dd60b6172df5a73daa403d1fc5b5e39169df40 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 25 Jan 2024 08:13:31 -0800
Subject: [PATCH] [RISCV] Add missing dependency check for Zvkb
---
https://github.com/4vtomat approved this pull request.
Thanks, LGTM~
https://github.com/llvm/llvm-project/pull/77889
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@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
OverloadedName += "_" + OverloadedSuffixStr.str();
// clang built-in function name, e.g. __builtin_rvv_vadd.
- std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name);
+ std::string
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77487
>From 84ea759c43d8e9cb450d95d00fd802be622153a2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 7 Jan 2024 18:10:59 -0800
Subject: [PATCH 1/2] [RISCV][clang] Optimize memory usage of intrinsic lookup
table
@@ -10,7 +10,8 @@
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1(
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT:call void @llvm.riscv.sf.vc.x.se.e64m1.i64.i64.i64(i64
3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[CONV:%.*]] = trunc i64
4vtomat wrote:
Since it only reduces about 160 of 54100 intrinsics generated, I have no
opinion on this, just left the final decision to others~
But if this PR is finally decided to be merged, please add some comments around
the code you added to explain, thanks!
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes () const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
-
https://github.com/4vtomat edited
https://github.com/llvm/llvm-project/pull/77487
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@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult ,
IdentifierInfo *II,
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes () const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
-
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes () const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
-
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