[clang] [clang][RISCV] Fix crash on VLS calling convention (PR #145489)

@@ -143,52 +143,82 @@ void __attribute__((riscv_vls_cc)) test_too_large(int32x64_t arg) {} // CHECK-LLVM: define dso_local riscv_vls_cc(256) void @test_too_large_256( noundef %arg.coerce) void __attribute__((riscv_vls_cc(256))) test_too_large_256(int32x64_t arg) {} -// CHECK

[clang] [RISCV] Remove required features zvfhmin/zvfbfmin from plain f16/bf16 intrinsics (PR #145891)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/145891 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support of Zibi experimental extension (PR #127463)

topperc wrote: > > > This adds the support of Zibi v0.1 experimental extension. > > > References: > > > > > > * > > > https://lf-riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan > > > > > > I cannot for the life of me find an actual specificati

[clang] [llvm] [RISCV] Fix typo in the description of xsfvfwmaccqqq. (PR #145771)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/145771 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Fix typo in the description of xsfvfwmaccqqq. (PR #145771)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/145771 None >From 620a09cdb999d07b82bb00185da7941dac35428c Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 25 Jun 2025 12:32:35 -0700 Subject: [PATCH] [RISCV] Fix typo in the description of xsfvfwmaccqqq. ---

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -2742,6 +2742,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, case RISCVOp::OPERAND_UIMM9_LSB000: Ok = isShiftedUInt<6, 3>(Imm); break; +case RISCVOp::OPERAND_UIMM9: topperc wrote: Use `CASE_OPERAND_U

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -2925,6 +2925,54 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base, return true; } +/// Similar to SelectAddrRegImm, except that the offset restricted for +/// nine bits. +bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base, +

[clang] [llvm] [RISCV] Add Support of RISCV Zibimm Experimental Extension (PR #127463)

topperc wrote: Please update RISCVUsage.rst and the release notes https://github.com/llvm/llvm-project/pull/127463 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add missing required features for Zvfbfmin intrinsics (PR #145646)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/145646 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -0,0 +1,40 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV32XMIPSPREFETCH +; RUN: llc -mtriple=riscv64 -mattr=+xmip

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -535,6 +535,19 @@ static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address, Inst.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } +template +static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, +

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -103,9 +109,41 @@ class SWPFormat let Inst{6-0} = OPC_CUSTOM_0.Value; } +// Prefetch format. +let hasSideEffects = 0, mayLoad = 1,mayStore = 1 in +class Mips_prefetch_ri +: RVInst { + bits<9> imm9; + bits<5> rs1; + bits<5> hint; + + let Inst{31 - 29} = 0b000; + l

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -2925,6 +2925,54 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base, return true; } +/// Similar to SelectAddrRegImm, except that the offset restricted for +/// nine bits. +bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base, +

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/145647 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -535,6 +535,19 @@ static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address, Inst.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } +template +static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, ---

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -103,9 +109,41 @@ class SWPFormat let Inst{6-0} = OPC_CUSTOM_0.Value; } +// Prefetch format. +let hasSideEffects = 0, mayLoad = 1,mayStore = 1 in +class Mips_prefetch_ri +: RVInst { + bits<9> imm9; + bits<5> rs1; + bits<5> hint; + + let Inst{31 - 29} = 0b000;

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -103,9 +109,41 @@ class SWPFormat let Inst{6-0} = OPC_CUSTOM_0.Value; } +// Prefetch format. +let hasSideEffects = 0, mayLoad = 1,mayStore = 1 in +class Mips_prefetch_ri +: RVInst { + bits<9> imm9; + bits<5> rs1; + bits<5> hint; + + let Inst{31 - 29} = 0b000; + l

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -103,9 +109,41 @@ class SWPFormat let Inst{6-0} = OPC_CUSTOM_0.Value; } +// Prefetch format. +let hasSideEffects = 0, mayLoad = 1,mayStore = 1 in +class Mips_prefetch_ri +: RVInst { + bits<9> imm9; + bits<5> rs1; + bits<5> hint; + + let Inst{31 - 29} = 0b000; + l

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -103,9 +109,41 @@ class SWPFormat let Inst{6-0} = OPC_CUSTOM_0.Value; } +// Prefetch format. +let hasSideEffects = 0, mayLoad = 1,mayStore = 1 in topperc wrote: ```suggestion let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in ``` https://github.com/ll

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -103,9 +109,41 @@ class SWPFormat let Inst{6-0} = OPC_CUSTOM_0.Value; } +// Prefetch format. +let hasSideEffects = 0, mayLoad = 1,mayStore = 1 in +class Mips_prefetch_ri +: RVInst { + bits<9> imm9; + bits<5> rs1; + bits<5> hint; + + let Inst{31 - 29} = 0b000; + l

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -103,9 +109,41 @@ class SWPFormat let Inst{6-0} = OPC_CUSTOM_0.Value; } +// Prefetch format. +let hasSideEffects = 0, mayLoad = 1,mayStore = 1 in +class Mips_prefetch_ri +: RVInst { + bits<9> imm9; + bits<5> rs1; + bits<5> hint; + + let Inst{31 - 29} = 0b000; + l

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -103,9 +109,41 @@ class SWPFormat let Inst{6-0} = OPC_CUSTOM_0.Value; } +// Prefetch format. +let hasSideEffects = 0, mayLoad = 1,mayStore = 1 in +class Mips_prefetch_ri +: RVInst { + bits<9> imm9; + bits<5> rs1; + bits<5> hint; + + let Inst{31 - 29} = 0b000; + l

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -535,6 +535,19 @@ static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address, Inst.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; } +template +static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, +

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -2925,6 +2925,54 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base, return true; } +/// Similar to SelectAddrRegImm, except that the offset restricted for +/// nine bits. +bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base, +

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/145647 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

@@ -1523,6 +1524,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return generateImmOutOfRangeError( Operands, ErrorInfo, 0, (1 << 8) - 8, "immediate must be a multiple of 8 bytes in the range"); + case Match_InvalidUImm9:

[clang] [clang][RISCV] Fix crash on VLS calling convention (PR #145489)

@@ -143,52 +143,82 @@ void __attribute__((riscv_vls_cc)) test_too_large(int32x64_t arg) {} // CHECK-LLVM: define dso_local riscv_vls_cc(256) void @test_too_large_256( noundef %arg.coerce) void __attribute__((riscv_vls_cc(256))) test_too_large_256(int32x64_t arg) {} -// CHECK

[clang] [clang][RISCV] Fix crash on VLS calling convention (PR #145489)

@@ -143,52 +143,82 @@ void __attribute__((riscv_vls_cc)) test_too_large(int32x64_t arg) {} // CHECK-LLVM: define dso_local riscv_vls_cc(256) void @test_too_large_256( noundef %arg.coerce) void __attribute__((riscv_vls_cc(256))) test_too_large_256(int32x64_t arg) {} -// CHECK

[clang] [clang][RISCV] Fix crash on VLS calling convention (PR #145489)

@@ -1329,6 +1329,19 @@ static llvm::Value *CreateCoercedLoad(Address Src, llvm::Type *Ty, llvm::TypeSize DstSize = CGF.CGM.getDataLayout().getTypeAllocSize(Ty); if (llvm::StructType *SrcSTy = dyn_cast(SrcTy)) { +if (Ty->isScalableTy() || Ty->isRISCVVectorTupleTy()) {

[clang] [clang][RISCV] Fix crash on VLS calling convention (PR #145489)

@@ -1412,6 +1425,21 @@ void CodeGenFunction::CreateCoercedStore(llvm::Value *Src, Address Dst, if (SrcTy != Dst.getElementType()) { if (llvm::StructType *DstSTy = dyn_cast(Dst.getElementType())) { + if (SrcTy->isScalableTy() || SrcTy->isRISCVVectorTupleT

[clang] [llvm] [RISCV] Add Support of RISCV Zibimm Experimental Extension (PR #127463)

@@ -0,0 +1,299 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibimm -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32I-ZIBIMM %s topperc wrote: Use a comm

[clang] [llvm] Revert "[RISCV] Remove B and Zbc extension from Andes series cpus." (PR #144402)

topperc wrote: > Since https://github.com/llvm/llvm-project/pull/144848 has landed, I reverted > this reverted commit by > https://github.com/llvm/llvm-project/commit/f78819aeef32e50ac3fec9a175b70a971b7c10e5. In the future use "Recommit" in the title instead of "Revert Revert". https://github

[clang] [llvm] [RISCV] Add Support of RISCV Zibimm Experimental Extension (PR #127463)

@@ -0,0 +1,48 @@ +//===-- RISCVInstrInfoZibimm.td - 'Zibimm' instructions --*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: A

[clang] [llvm] [RISCV] Add Support of RISCV Zibimm Experimental Extension (PR #127463)

@@ -350,6 +350,18 @@ static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, return decodeUImmOperand(Inst, Imm, Address, Decoder); } +template +static DecodeStatus decodeUImmZibimmOperand(MCInst &Inst, uint32_t Imm, +

[clang] [llvm] [RISCV] Add Support of RISCV Zibimm Experimental Extension (PR #127463)

@@ -0,0 +1,48 @@ +//===-- RISCVInstrInfoZibimm.td - 'Zibimm' instructions --*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: A

[clang] [llvm] [RISCV] Add Support of RISCV Zibimm Experimental Extension (PR #127463)

@@ -350,6 +350,18 @@ static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, return decodeUImmOperand(Inst, Imm, Address, Decoder); } +template topperc wrote: Drop the template and replace `N` with 5 in the function. https://github.com/l

[clang] [llvm] [RISCV] Remove B and Zbc extension from Andes series cpus. (PR #144022)

topperc wrote: > > > Not related to this PR, but I'd like to raise the question here: > > > > For configurable cores, what is the best way to specify the features? > > > `-mcpu` is meant to support the base configuration, but how can we > > > specify the additional optional extensions? Apparen

[clang] [llvm] [RISCV] Fix incorrect predicates for fp16 permutation intrinsics (PR #144063)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/144063 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Fix incorrect predicates for fp16 permutation intrinsics (PR #144063)

@@ -7405,8 +7405,12 @@ defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllInteger defm : VPatBinaryV_VX<"int_riscv_vslide1up", "PseudoVSLIDE1UP", AllIntegerVectors>; defm : VPatBinaryV_VX<"int_riscv_vslide1down", "PseudoVSLIDE1DOWN", AllIntegerVectors>;

[clang] [llvm] [Transforms] Implement always_specialize attribute lowering (PR #143983)

@@ -0,0 +1,324 @@ +//===- AlwaysSpecializer.cpp - implementation of always_specialize ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Remove B and Zbc extension from Andes series cpus. (PR #144022)

topperc wrote: > I think this feature is really tough, the arm/aarch64 backends have got too > much complexity from similar features, mostly because their cpus have all > their optional features enabled by default. > > I think if you can only enable additional extensions, that proposed syntax

[clang] [clang][docs][RISCV] Pre-pend the HelpText for -mrvv-vector-bits into the DocBrief. (PR #144128)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/144128 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Fix incorrect predicates for fp16 permutation intrinsics (PR #144063)

@@ -7405,8 +7405,12 @@ defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllInteger defm : VPatBinaryV_VX<"int_riscv_vslide1up", "PseudoVSLIDE1UP", AllIntegerVectors>; defm : VPatBinaryV_VX<"int_riscv_vslide1down", "PseudoVSLIDE1DOWN", AllIntegerVectors>;

[clang] [RISCV] Use StringRef for RequiredExtensions in RVVIntrinsicDef (PR #143503)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/143503 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Cache required extensions string for RVVIntrinsicDef (PR #143503)

@@ -385,7 +390,8 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic( uint32_t Index = IntrinsicList.size(); assert(IntrinsicList.size() == (size_t)Index && "Intrinsics indices overflow."); - IntrinsicList.push_back({BuiltinName, Record.RequiredExtensions, Signatu

[clang] [llvm][RISCV] Handle required features of intrinsic correctly (PR #143062)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/143062 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm][RISCV] Handle required features of intrinsic correctly (PR #143062)

@@ -540,7 +494,7 @@ struct RVVIntrinsicRecord { const char *OverloadedName; // Required target features for this intrinsic. - RequiredExtensionBits RequiredExtensions; + std::string RequiredExtensions; topperc wrote: Can this be `const char *RequiredExt

[clang] [llvm] [llvm][RISCV] Make zvknhb imply zvknha (PR #142896)

topperc wrote: @4vtomat you did the opposite of this in 65dc96c2cfa480b070c7913ac5e313c98ca96520. What changed now? https://github.com/llvm/llvm-project/pull/142896 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin

[clang] [llvm] [RISCV] Add support for -mtune=andes-45-series (PR #142900)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/142900 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Implement intrinsics for XAndesVDot (PR #141441)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/141441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Handle target features correctly in CheckBuiltinFunctionCall (PR #141548)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/141548 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MC layer support for XSfmm*. (PR #133031)

@@ -2331,6 +2337,65 @@ bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) { "e[8|16|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]"); } +ParseStatus RISCVAsmParser::parseXSfmmVType(OperandVector &Operands) { + SMLoc S = getLoc(); + + unsigned Widen = 0; + unsigned SE

[clang] [llvm] [RISCV] Add MC layer support for XSfmm*. (PR #133031)

topperc wrote: > I still get compiler error for the above case, but with additional error > message: > > ``` > fatal error: error in backend: Invalid size request on a scalable vector. > PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ > and include the crash backtrac

[clang] [RISCV] Implement intrinsics for XAndesVPackFPH (PR #140007)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/140007 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MC layer support for XSfmm*. (PR #133031)

topperc wrote: Ping. Any further comments? https://github.com/llvm/llvm-project/pull/133031 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MC layer support for XSfmm*. (PR #133031)

topperc wrote: > > Is the issue really related to this PR? Why would a MC change cause CodeGen > > errors? Is it because uncommon extension combinations? > > I've played around with the -march flag a bit more, and it doesn't seem to be > the main culprit here. For example, even using > `-marc

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/139369 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes XAndesVDot (Andes Vector Dot Product) extension. (PR #139849)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/139849 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Improve casting between i1 scalable vectors and i8 fixed vectors for -mrvv-vector-bits (PR #139190)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/139190 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Improve casting between i1 scalable vectors and i8 fixed vectors for -mrvv-vector-bits (PR #139190)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/139190 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Improve casting between i1 scalable vectors and i8 fixed vectors for -mrvv-vector-bits (PR #139190)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/139190 >From 86692b0229da44dce5321b00c8409e50de86efaf Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 8 May 2025 15:13:47 -0700 Subject: [PATCH 1/2] [RISCV] Improve casting between i1 scalable vectors and i8 fi

[clang] [RISCV] Improve casting between i1 scalable vectors and i8 fixed vectors for -mrvv-vector-bits (PR #139190)

@@ -1366,19 +1366,29 @@ static llvm::Value *CreateCoercedLoad(Address Src, llvm::Type *Ty, // If we are casting a fixed i8 vector to a scalable i1 predicate // vector, use a vector insert and bitcast the result. if (ScalableDstTy->getElementType()->isIntegerT

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,151 @@ +//===-- RISCVInstrInfoQ.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,151 @@ +//===-- RISCVInstrInfoQ.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -674,6 +681,9 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { Opcode = RISCV::FSD; IsScalableVector = false; + } else if (RISCV::FPR128RegClass.hasSubClassEq(RC)) { topperc

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,151 @@ +//===-- RISCVInstrInfoQ.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -599,6 +599,13 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, return; } + if (RISCV::FPR128RegClass.contains(DstReg, SrcReg)) { topperc wrote: This isn't an MC layer change and can't be tested. https://github.com/llvm/llvm-project/pull

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -766,6 +776,9 @@ void RISCVInstrInfo::loadRegFromStackSlot( } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { Opcode = RISCV::FLD; IsScalableVector = false; + } else if (RISCV::FPR128RegClass.hasSubClassEq(RC)) { topperc wrote: This isn't an M

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

topperc wrote: Add to the RISC-V section of the clang release notes? https://github.com/llvm/llvm-project/pull/139519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Improve casting between i1 scalable vectors and i8 fixed vectors for -mrvv-vector-bits (PR #139190)

@@ -1476,8 +1486,14 @@ CoerceScalableToFixed(CodeGenFunction &CGF, llvm::FixedVectorType *ToTy, // If we are casting a scalable i1 predicate vector to a fixed i8 // vector, first bitcast the source. if (FromTy->getElementType()->isIntegerTy(1) && - FromTy->getElemen

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -147,6 +147,13 @@ def ntl_load : RISCVBuiltin<"void(...)">; def ntl_store : RISCVBuiltin<"void(...)">; } // Features = "zihintntl", Attributes = [CustomTypeChecking] +//===--===// +// Zihintpause extension.

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,168 @@ +//===-- RISCVInstrInfoF.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,168 @@ +//===-- RISCVInstrInfoF.td - RISC-V 'Q' instructions ---*- tablegen -*-===// topperc wrote: File name needs to be updated https://github.com/llvm/llvm-project/pull/139369 ___ cfe-commits mailing

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -462,6 +474,12 @@ def FPR64C : RISCVRegisterClass<[f64], 64, (add (sequence "F%u_D", 8, 9) )>; +def FPR128 : RISCVRegisterClass< + [f128], 128, topperc wrote: Format this the same was as FPR64? https://github.com/llvm/llvm-project/pull/1

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,168 @@ +//===-- RISCVInstrInfoF.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,168 @@ +//===-- RISCVInstrInfoF.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,168 @@ +//===-- RISCVInstrInfoF.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,168 @@ +//===-- RISCVInstrInfoF.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,168 @@ +//===-- RISCVInstrInfoF.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -45,6 +45,13 @@ class RISCVReg64 let SubRegIndices = [sub_32]; } +def sub_64 : SubRegIndex<64>; +class RISCVReg128 +: RISCVRegWithSubRegshttps://github.com/llvm/llvm-project/pull/139369 ___ cfe-commits mailing list cfe-commi

[clang] [llvm] [RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension. (PR #138827)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/138827 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [CodeGen][RISCV] Use vscale_range to handle more fixed<->scalable casts of i1 vectors. (PR #138378)

topperc wrote: Replaced with #139190 https://github.com/llvm/llvm-project/pull/138378 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [CodeGen][RISCV] Use vscale_range to handle more fixed<->scalable casts of i1 vectors. (PR #138378)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/138378 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Improve casting between i1 scalable vectors and i8 fixed vect… (PR #139190)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/139190 …ors for -mrvv-vector-bits For i1 vectors, we used an i8 fixed vector as the storage type. If the known minimum number of elements of the scalable vector type is less than 8, we were doing the cast through mem

[clang] [RISCV] Improve casting between i1 scalable vectors and i8 fixed vect… (PR #139190)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/139190 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Improve casting between i1 scalable vectors and i8 fixed vectors for -mrvv-vector-bits (PR #139190)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/139190 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [CodeGen][RISCV] Use vscale_range to handle more fixed<->scalable casts of i1 vectors. (PR #138378)

https://github.com/topperc converted_to_draft https://github.com/llvm/llvm-project/pull/138378 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [CodeGen][RISCV] Use vscale_range to handle more fixed<->scalable casts of i1 vectors. (PR #138378)

topperc wrote: I have a different idea I want to try. Moving to draft. https://github.com/llvm/llvm-project/pull/138378 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [CodeGen][RISCV] Use vscale_range to handle more fixed<->scalable casts of i1 vectors. (PR #138378)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/138378 RISC-V with -mrvv-vector-bits-min supports giving a size to our scalable vector types. To do this, we represent the vector as a fixed vector in memory and need to cast back and force to scable vectors. For i1

[clang] [llvm] [IRBuilder] Add versions of createInsertVector/createExtractVector that take a uint64_t index. (PR #138324)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/138324 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [IRBuilder] Add versions of createInsertVector/createExtractVector that take a uint64_t index. (PR #138324)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/138324 Most callers want a constant index. Instead of making every caller create a ConstantInt, we can do it in IRBuilder. This is similar to createInsertElement/createExtractElement. >From 827f973d34f46625cfadf56776

[clang] [llvm] [LLVM][SROA] Teach SROA how to "bitcast" between fixed and scalable vectors. (PR #130973)

@@ -26,11 +26,15 @@ typedef vbool64_t fixed_bool64_t __attribute__((riscv_rvv_vector_bits(__riscv_v_ // // CHECK-128-LABEL: @call_bool32_ff( // CHECK-128-NEXT: entry: +// CHECK-128-NEXT:[[SAVED_VALUE:%.*]] = alloca <1 x i8>, align 1 topperc wrote: Before

[clang] [llvm] [RISCV] Add MC layer support for XSfmm*. (PR #133031)

@@ -1197,6 +1197,73 @@ def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">, AssemblerPredicate<(all_of FeatureVendorXSfvcp), "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">; +def FeatureVendorX

[clang] [llvm] [RISCV] Add MC layer support for XSfmm*. (PR #133031)

@@ -1197,6 +1197,73 @@ def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">, AssemblerPredicate<(all_of FeatureVendorXSfvcp), "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">; +def FeatureVendorX

[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, TuneVXRMPipelineFlush, TunePostRAScheduler]>; +def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSched

[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, TuneVXRMPipelineFlush, TunePostRAScheduler]>; +def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSched

[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, TuneVXRMPipelineFlush, TunePostRAScheduler]>; +def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSched

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/135110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] SiFive CLIC Support (PR #132481)

@@ -200,6 +203,149 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, CFIInstBuilder(MBB, MI, MachineInstr::FrameDestroy).buildRestore(SCSPReg); } +// Insert instruction to swap mscratchsw with sp +static void emitSiFiveCLICStackSwap(MachineFunction

[clang] [llvm] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (PR #136842)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/136842 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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