[clang] 562c27e - [RISCV] Fix accidentally lower case REQUIRES directive in vfncvtbf16-out-of-range.c. NFC

Author: Craig Topper Date: 2025-08-28T22:45:32-07:00 New Revision: 562c27e478744322ea5475a5f135cc030dce799e URL: https://github.com/llvm/llvm-project/commit/562c27e478744322ea5475a5f135cc030dce799e DIFF: https://github.com/llvm/llvm-project/commit/562c27e478744322ea5475a5f135cc030dce799e.diff

[clang] [RISCV] Verify vfwmaccbf16 and vfncvtbf16 FRM argument in SemaRISCV::CheckBuiltinFunctionCall. (PR #155710)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/155710 >From 41c79fa197820c96637f03c8c2f9cdcaeb3ff5cc Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 27 Aug 2025 15:36:08 -0700 Subject: [PATCH 1/2] [RISCV] Verify vfwmaccbf16 and vfncvtbf16 FRM argument in Se

[clang] [llvm] [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (PR #155747)

@@ -166,7 +181,7 @@ def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)), } let Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0, - DecoderNamespace = "Xmipslsp" in { + DecoderNamespace = "XMIPS" in {

[clang] [llvm] [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (PR #155747)

@@ -1396,20 +1396,27 @@ def HasVendorXMIPSCMov AssemblerPredicate<(all_of FeatureVendorXMIPSCMov), "'Xmipscmov' ('mips.ccmov' instruction)">; def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">; + def FeatureVendorXMIPSLSP : RISCVExten

[clang] [llvm] [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (PR #155747)

@@ -146,7 +161,7 @@ let Predicates = [HasVendorXMIPSCBOP] in { } let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0, - DecoderNamespace = "Xmipscmov" in { + DecoderNamespace = "XMIPS" in { topp

[clang] [llvm] [RISCV] Support XSfmm C intrinsics (PR #143070)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/143070 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support XSfmm C intrinsics (PR #143070)

@@ -679,6 +685,50 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, return CheckVSetVL(1, 2); case RISCVVector::BI__builtin_rvv_vsetvlimax: return CheckVSetVL(0, 1); + case RISCVVector::BI__builtin_rvv_sf_vsettnt: + case RISCVVector::BI__builtin_rvv

[clang] [llvm] [RISCV] Support XSfmm C intrinsics (PR #143070)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/143070 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (PR #155747)

@@ -125,10 +125,25 @@ class Mips_prefetch_ri let Inst{6-0} = OPC_CUSTOM_0.Value; } +// MIPS Ext Insns Fromat. +let hasSideEffects = 1, mayLoad = 0, +mayStore = 0 in class MIPSExtInst_ri shimm5, string opcodestr> topperc wrote: ```suggestion let hasSideE

[clang] [llvm] [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (PR #155747)

@@ -125,10 +125,25 @@ class Mips_prefetch_ri let Inst{6-0} = OPC_CUSTOM_0.Value; } +// MIPS Ext Insns Fromat. +let hasSideEffects = 1, mayLoad = 0, +mayStore = 0 in class MIPSExtInst_ri shimm5, string opcodestr> +: RVInstIShift<0b0, 0b001, OPC_OP_IMM, (outs), (in

[clang] [llvm] [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (PR #155747)

@@ -125,10 +125,25 @@ class Mips_prefetch_ri let Inst{6-0} = OPC_CUSTOM_0.Value; } +// MIPS Ext Insns Fromat. topperc wrote: What does "Ext" mean here? https://github.com/llvm/llvm-project/pull/155747 ___ cfe-com

[clang] [llvm] [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (PR #155747)

@@ -1,9 +1,27 @@ -# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+Xmipscmov,+xmipscbop,+xmipsexectl -M no-aliases -show-encoding \ topperc wrote: ```s

[clang] [llvm] [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (PR #155747)

@@ -125,10 +125,25 @@ class Mips_prefetch_ri let Inst{6-0} = OPC_CUSTOM_0.Value; } +// MIPS Ext Insns Fromat. topperc wrote: ```suggestion // MIPS Ext Insns Format. ``` https://github.com/llvm/llvm-project/pull/155747 __

[clang] [llvm] [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (PR #155747)

@@ -121,7 +121,8 @@ def MIPS_P8700 : RISCVProcessorModel<"mips-p8700", FeatureStdExtZicsr, FeatureVendorXMIPSCMov, FeatureVendorXMIPSLSP, -

[clang] [RISCV] Verify vfwmaccbf16 and vfncvtbf16 FRM argument in SemaRISCV::CheckBuiltinFunctionCall. (PR #155710)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/155710 >From 41c79fa197820c96637f03c8c2f9cdcaeb3ff5cc Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 27 Aug 2025 15:36:08 -0700 Subject: [PATCH] [RISCV] Verify vfwmaccbf16 and vfncvtbf16 FRM argument in SemaRI

[clang] [RISCV] Verify vfwmaccbf16 and vfncvtbf16 FRM argument in SemaRISCV::CheckBuiltinFunctionCall. (PR #155710)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/155710 We need to check that the FRM value is an integer constant expression with value 0-4. >From 41c79fa197820c96637f03c8c2f9cdcaeb3ff5cc Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 27 Aug 2025 15:36:08

[clang] [llvm] [RISCV] Implement MC support for Zvfbfa extension (PR #151106)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/151106 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Implement MC support for Zvfbfa extension (PR #151106)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/151106 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Implement MC support for Zvfbfa extension (PR #151106)

topperc wrote: I think we should accept this patch. The spec has is in internal review at RVI https://lists.riscv.org/g/tech-unprivileged/message/1085 as of last week. What's here looks pretty minimal and wouldn't be hard to remove if RVI changes direction. https://github.com/llvm/llvm-projec

[clang] [llvm] [RISCV] Support ZVqdot Codegen and C intrinsics (PR #154915)

@@ -52,10 +52,71 @@ let Predicates = [HasStdExtZvqdotq], mayLoad = 0, mayStore = 0, defm PseudoVQDOT : VPseudoVQDOT_VV_VX; defm PseudoVQDOTU : VPseudoVQDOT_VV_VX; defm PseudoVQDOTSU : VPseudoVQDOT_VV_VX; + // VQDOTUS does not have a VV variant + foreach m = MxListVF4 i

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/154906 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (PR #154906)

@@ -20,6 +20,958 @@ using namespace clang; using namespace CodeGen; using namespace llvm; +// The 0th bit simulates the `vta` of RVV +// The 1st bit simulates the `vma` of RVV +static constexpr unsigned RVV_VTA = 0x1; +static constexpr unsigned RVV_VMA = 0x2; + +// RISC-V Vect

[clang] [llvm] [RISCV] Support ZVqdot Codegen and C intrinsics (PR #154915)

@@ -52,10 +52,72 @@ let Predicates = [HasStdExtZvqdotq], mayLoad = 0, mayStore = 0, defm PseudoVQDOT : VPseudoVQDOT_VV_VX; defm PseudoVQDOTU : VPseudoVQDOT_VV_VX; defm PseudoVQDOTSU : VPseudoVQDOT_VV_VX; + // VQDOTUS does not have a VV variant + foreach m = MxListVF4 i

[clang] [llvm] [RISCV] Support ZVqdot Codegen and C intrinsics (PR #154915)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/154915 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support ZVqdot Codegen and C intrinsics (PR #154915)

@@ -52,10 +52,72 @@ let Predicates = [HasStdExtZvqdotq], mayLoad = 0, mayStore = 0, defm PseudoVQDOT : VPseudoVQDOT_VV_VX; defm PseudoVQDOTU : VPseudoVQDOT_VV_VX; defm PseudoVQDOTSU : VPseudoVQDOT_VV_VX; + // VQDOTUS does not have a VV variant + foreach m = MxListVF4 i

[clang] [llvm] [RISCV] Support ZVqdot Codegen and C intrinsics (PR #154915)

@@ -0,0 +1,120 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \ +// RUN

[clang] [llvm] [RISCV] Support ZVqdot Codegen and C intrinsics (PR #154915)

@@ -52,10 +52,72 @@ let Predicates = [HasStdExtZvqdotq], mayLoad = 0, mayStore = 0, defm PseudoVQDOT : VPseudoVQDOT_VV_VX; defm PseudoVQDOTU : VPseudoVQDOT_VV_VX; defm PseudoVQDOTSU : VPseudoVQDOT_VV_VX; + // VQDOTUS does not have a VV variant + foreach m = MxListVF4 i

[clang] 8cb6bfe - [RISCV] Reduce ManualCodeGen for RVV intrinsics with rounding mode. NFC

Author: Craig Topper Date: 2025-08-20T17:53:46-07:00 New Revision: 8cb6bfe05a26e40dee21d6107655baacc03540a9 URL: https://github.com/llvm/llvm-project/commit/8cb6bfe05a26e40dee21d6107655baacc03540a9 DIFF: https://github.com/llvm/llvm-project/commit/8cb6bfe05a26e40dee21d6107655baacc03540a9.diff

[clang] [llvm] [RISCV] Support Remaining P Extension Instructions for RV32/64 (PR #150379)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/150379 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove experimental from Smctr and Ssctr. (PR #153903)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/153903 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove experimental from Smctr and Ssctr. (PR #153903)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/153903 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove experimental from Smctr and Ssctr. (PR #153903)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/153903 None >From 30b3e701ff94691ff55aeb1297890eac71b59857 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 15 Aug 2025 16:31:29 -0700 Subject: [PATCH] [RISCV] Remove experimental from Smctr and Ssctr. --- ...

[clang] [llvm] [RISCV] Support Remaining P Extension Instructions for RV32/64 (PR #150379)

@@ -559,3 +559,204 @@ let Predicates = [HasStdExtP, IsRV64] in { def PPACKT_W: RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">; def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">; } // Predicates = [HasStdExtP, IsRV64] +let Predicates = [HasStdExtP] in { + def

[clang] [llvm] [RISCV] Support Remaining P Extension Instructions for RV32/64 (PR #150379)

@@ -559,3 +559,204 @@ let Predicates = [HasStdExtP, IsRV64] in { def PPACKT_W: RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">; def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">; } // Predicates = [HasStdExtP, IsRV64] +let Predicates = [HasStdExtP] in { + def

[clang] [llvm] [RISCV] Support Remaining P Extension Instructions for RV32/64 (PR #150379)

@@ -559,3 +559,204 @@ let Predicates = [HasStdExtP, IsRV64] in { def PPACKT_W: RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">; def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">; } // Predicates = [HasStdExtP, IsRV64] +let Predicates = [HasStdExtP] in { + def

[clang] [llvm] [RISCV] Support Remaining P Extension Instructions for RV32/64 (PR #150379)

@@ -559,3 +559,204 @@ let Predicates = [HasStdExtP, IsRV64] in { def PPACKT_W: RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">; def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">; } // Predicates = [HasStdExtP, IsRV64] +let Predicates = [HasStdExtP] in { + def

[clang] [llvm] [RISCV] Support Remaining P Extension Instructions for RV32/64 (PR #150379)

@@ -559,3 +559,204 @@ let Predicates = [HasStdExtP, IsRV64] in { def PPACKT_W: RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">; def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">; } // Predicates = [HasStdExtP, IsRV64] +let Predicates = [HasStdExtP] in { ---

[clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)

@@ -0,0 +1,1100 @@ +//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: A

[clang] [llvm] [RISCV][llvm] Support fixed-length vector inline assembly constraints (PR #150724)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/150724 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support Base P RV32/64 Instructions (PR #150379)

topperc wrote: I missed this patch in my email. I posted #153458 for the other shift instructions. I used RVPShiftD_ri instead of RVPShiftD_ri. D would be the usual suffix for "doubleword" or 64 bits. https://github.com/llvm/llvm-project/pull/150379

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

=?utf-8?b?5p6X5YWL?= ,xuqian ,xuqian Message-ID: In-Reply-To: https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/151706 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[clang] [RISCV] Add -march=unset to cancel and ignore a previous -march. (PR #148321)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/148321 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add -march=unset to cancel and ignore a previous -march. (PR #148321)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/148321 >From 9521bd783966635f3219ac02e3fe43ed33294546 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 11 Jul 2025 17:42:49 -0700 Subject: [PATCH 1/4] [RISCV] Add -march=unset to cancel and ignore a previous -ma

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/151706 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

@@ -0,0 +1,141 @@ +//===-- RISCVInstrInfoXSMTVDot.td --*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [clang][RISCV][Zicfilp] Force user to use `-mcf-branch-label-scheme=unlabeled` (PR #152122)

@@ -356,6 +356,8 @@ def err_opt_not_valid_without_opt : Error< "option '%0' cannot be specified without '%1'">; def err_opt_not_valid_on_target : Error< "option '%0' cannot be specified on this target">; +def err_opt_unsupported_with_sugguest : Error< toppe

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

@@ -0,0 +1,141 @@ +//===-- RISCVInstrInfoXSMTVDot.td - SpacemiT Vector Dot Product *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identi

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/151706 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

@@ -0,0 +1,141 @@ +//===-- RISCVInstrInfoXSMTVDot.td - SpacemiT Vector Dot Product *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identi

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

@@ -0,0 +1,141 @@ +//===-- RISCVInstrInfoXSMTVDot.td --*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

@@ -0,0 +1,141 @@ +//===-- RISCVInstrInfoXSMTVDot.td --*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

@@ -0,0 +1,141 @@ +//===-- RISCVInstrInfoXSMTVDot.td - SpacemiT Vector Dot Product *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identi

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

@@ -344,6 +344,17 @@ static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } +static DecodeStatus DecodeVREvenRegisterClass(MCInst &Inst, uint32_t RegNo, topperc wrote: Is this called. I don't see VREven

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

@@ -0,0 +1,141 @@ +//===-- RISCVInstrInfoXSMTVDot.td - SpacemiT Vector Dot Product *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identi

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

@@ -0,0 +1,141 @@ +//===-- RISCVInstrInfoXSMTVDot.td - SpacemiT Vector Dot Product *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identi

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

@@ -0,0 +1,141 @@ +//===-- RISCVInstrInfoXSMTVDot.td - SpacemiT Vector Dot Product *- tablegen -*-===// topperc wrote: This line should not exceed 80 characters. https://github.com/llvm/llvm-project/pull/151706 __

[clang] [llvm] [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (PR #151706)

@@ -0,0 +1,141 @@ +//===-- RISCVInstrInfoXSMTVDot.td - SpacemiT Vector Dot Product *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identi

[clang] [llvm] [RISCV] Implement MC support for Zvfbfa extension (PR #151106)

@@ -17,15 +17,15 @@ // Instructions //===--===// -let Predicates = [HasStdExtZvfbfmin], Constraints = "@earlyclobber $vd", +let Predicates = [HasStdExtZvfbfminOrZvfbfa], Constraints = "@earlyclobber $vd",

[clang] [llvm] [RISCV] Implement MC support for Zvfbfa extension (PR #151106)

@@ -216,9 +216,12 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Imm = MI->getOperand(OpNo).getImm(); // Print the raw immediate for reserved values: vlmul[2:

[clang] [llvm] [RISCV] Implement MC support for Zvfbfa extension (PR #151106)

@@ -17,15 +17,15 @@ // Instructions //===--===// -let Predicates = [HasStdExtZvfbfmin], Constraints = "@earlyclobber $vd", +let Predicates = [HasStdExtZvfbfminOrZvfbfa], Constraints = "@earlyclobber $vd", --

[clang] [llvm] [RISCV] Implement MC support for Zvfbfa extension (PR #151106)

@@ -153,12 +153,13 @@ namespace RISCVVType { // // Bits | Name | Description // -++ +// 8| altfmt | Alternative format for bf16 // 7| vma| Vector mask agnostic // 6| vta| Vec

[clang] [llvm] [RISCV][llvm] Support fixed-length vector inline assembly constraints (PR #150724)

@@ -0,0 +1,39 @@ +// REQUIRES: riscv-registered-target + +// RUN: %clang_cc1 -triple riscv32 -target-feature +v \ +// RUN: -mvscale-min=2 -mvscale-max=2 -O2 -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -

[clang] [llvm] [RISCV][llvm] Support fixed-length vector inline assembly constraints (PR #150724)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/150724 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][llvm] Support fixed-length vector inline assembly constraints (PR #150724)

@@ -23146,10 +23152,24 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, &RISCV::VRN2M4NoV0RegClass}) { if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy)) return std::make_pair(0U, RC); + + if (VT.isFixedLengthVector(

[clang] [llvm] [RISCV][llvm] Support fixed-length vector inline assembly constraints (PR #150724)

@@ -0,0 +1,39 @@ +// REQUIRES: riscv-registered-target + +// RUN: %clang_cc1 -triple riscv32 -target-feature +v \ +// RUN: -mvscale-min=2 -mvscale-max=2 -O2 -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -

[clang] [llvm] [RISCV][llvm] Support fixed-length vector inline assembly constraints (PR #150724)

@@ -23146,10 +23152,24 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, &RISCV::VRN2M4NoV0RegClass}) { if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy)) return std::make_pair(0U, RC); + + if (VT.isFixedLengthVector(

[clang] [llvm] [RISCV][llvm] Support fixed-length vector inline assembly constraints (PR #150724)

@@ -24097,12 +24122,17 @@ SDValue RISCVTargetLowering::joinRegisterPartsIntoValue( return Val; } - if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { + if ((ValueVT.isScalableVector() || ValueVT.isFixedLengthVector()) && + PartVT.isScalableVector()) {

[clang] [RISCV] Add negative pre-defined macro test for XSfmm* extension. NFC. (PR #150596)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/150596 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support XSfmm C intrinsics (PR #143070)

@@ -679,6 +685,50 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, return CheckVSetVL(1, 2); case RISCVVector::BI__builtin_rvv_vsetvlimax: return CheckVSetVL(0, 1); + case RISCVVector::BI__builtin_rvv_sf_vsettnt: + case RISCVVector::BI__builtin_rvv

[clang] [clang][RISCV] Fix crash on VLS calling convention (PR #145489)

@@ -244,6 +244,15 @@ ABIInfo::getOptimalVectorMemoryType(llvm::FixedVectorType *T, return T; } +llvm::Value *ABIInfo::CreateCoercedLoad(Address SrcAddr, const ABIArgInfo &AI, +CodeGenFunction &CGF) const { + return nullptr; +} +void

[clang] [llvm] [RISCV] Implement Builtins for XAndesBFHCvt extension. (PR #148804)

topperc wrote: Can't we use the fptrunc and fpext IR instructions for this? https://github.com/llvm/llvm-project/pull/148804 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Prefix mcpu/mtune/march/mabi with '-' in comments. NFC (PR #148723)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/148723 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension (PR #148563)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/148563 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add -march=unset to cancel and ignore a previous -march. (PR #148321)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/148321 >From 9521bd783966635f3219ac02e3fe43ed33294546 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 11 Jul 2025 17:42:49 -0700 Subject: [PATCH 1/3] [RISCV] Add -march=unset to cancel and ignore a previous -ma

[clang] [RISCV] Add -march=unset to cancel and ignore a previous -march. (PR #148321)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/148321 >From 9521bd783966635f3219ac02e3fe43ed33294546 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 11 Jul 2025 17:42:49 -0700 Subject: [PATCH 1/2] [RISCV] Add -march=unset to cancel and ignore a previous -ma

[clang] [RISCV] Add -march=unset to cancel and ignore a previous -march. (PR #148321)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/148321 -mcpu is used to determine the ISA string if an explicit -march is not present on the command line. If there is a -march present it always has priority over -mcpu regardless of where it appears in the command l

[clang] [RISCV] Use source element type for the zero constant in IR for vwcvt intrinsic. (PR #148023)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/148023 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

@@ -1829,6 +1844,9 @@ Triple Triple::get32BitArchVariant() const { case Triple::ppc64le:T.setArch(Triple::ppcle); break; case Triple::renderscript64: T.setArch(Triple::renderscript32); break; case Triple::riscv64:T.setArch(Triple::riscv32); break; + cas

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

@@ -237,7 +241,10 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) { case wasm64: return "wasm"; case riscv32: - case riscv64: return "riscv"; + case riscv64: + case riscv32be: + case riscv64be: +return "riscv"; topperc wrote: Follow

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

@@ -63,6 +63,10 @@ StringRef Triple::getArchTypeName(ArchType Kind) { case renderscript64: return "renderscript64"; case riscv32:return "riscv32"; case riscv64:return "riscv64"; + case riscv32be: topperc wrote: Follow the existing format

[clang] [RISCV] Correct type lowering of struct of fixed-vector array in VLS (PR #147173)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/147173 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add missing intrinsicis vrgatherei16/vslideup/vslidedown support for Zvfbfmin (PR #146309)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/146309 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add MC support of Zibi experimental extension (PR #127463)

@@ -0,0 +1,42 @@ +//===-- RISCVInstrInfoZibi.td - 'Zibi' instructions --*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [RISCV][MC] Add MC support of Zibi experimental extension (PR #127463)

@@ -0,0 +1,42 @@ +//===-- RISCVInstrInfoZibi.td - 'Zibi' instructions --*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache

[clang] [llvm] [RISCV] Remove implied extension Zvfhmin for XAndesVPackFPH (PR #146861)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/146861 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

https://github.com/topperc approved this pull request. LGTM but please wait for @lenary to approve too https://github.com/llvm/llvm-project/pull/145647 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listi

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