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https://github.com/llvm/llvm-project/pull/143124
An error message will be emitted if the wrong value is passed to
-mstack-alignment option.
>From 688405f851d3685e588b4797314377a1d5d5c124 Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Fri, 6 Jun 2025 18:21:30 +0
fzou1 wrote:
> > Looks like this breaks tests on macOS:
> > http://45.33.8.238/macm1/107398/step_6.txt
> > Please take a look and revert for now if it takes a while to fix.
>
> Thank you. I've reproduced this issue on MacOS and updated PR #141486 to fix
> it.
@nico / @rorth , The PR #141486 h
https://github.com/fzou1 closed https://github.com/llvm/llvm-project/pull/141486
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fzou1 wrote:
> Looks like this breaks tests on macOS:
> http://45.33.8.238/macm1/107398/step_6.txt
>
> Please take a look and revert for now if it takes a while to fix.
Thank you. I've reproduced this issue on MacOS and updated PR #141486 to fix it.
https://github.com/llvm/llvm-project/pull/1
https://github.com/fzou1 edited https://github.com/llvm/llvm-project/pull/141486
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>From 5f839ebc0d21f393b30821b1df44d066e4b11d2b Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Mon, 26 May 2025 20:16:34 +0800
Subject: [PATCH 1/2] [Driver][X86] Fix LIT test failure on Solaris OS + AMD64
CPU.
The
fzou1 wrote:
> > This patch broke the [Solaris/amd64
> > buildbot](https://lab.llvm.org/staging/#/builders/120/builds/8977). I
> > suspect the test should use `--target=i386-pc-windows` instead of just
> > `i386`?
>
> Sorry for that. I've uploaded a PR (#141486) to fix that. But I didn't veri
fzou1 wrote:
> This patch broke the [Solaris/amd64
> buildbot](https://lab.llvm.org/staging/#/builders/120/builds/8977). I suspect
> the test should use `--target=i386-pc-windows` instead of just `i386`?
Sorry for that. I've uploaded a PR (#141486) to fix that. But I didn't verify
that since
https://github.com/fzou1 created
https://github.com/llvm/llvm-project/pull/141486
The LIT test is introduced by https://github.com/llvm/llvm-project/pull/140874.
>From 5f839ebc0d21f393b30821b1df44d066e4b11d2b Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Mon, 26 May 2025 20:16:34 +0800
Subject
https://github.com/fzou1 closed https://github.com/llvm/llvm-project/pull/140874
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fzou1 wrote:
@KanRobert , any further comments?
https://github.com/llvm/llvm-project/pull/140874
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@@ -6679,8 +6679,13 @@ def mapx_features_EQ : CommaJoined<["-"],
"mapx-features=">, Group,
Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">, Visibility<[ClangOption,
CLOption, FlangOption]>;
def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
HelpTex
@@ -135,3 +135,53 @@
void f(void) {
}
+
+
+// RUN: not %clang_cl -### --target=i386 -mapx-features=ndd %s 2>&1 |
FileCheck --check-prefix=NON-APX %s
+// RUN: not %clang_cl -### --target=i386 -mapxf %s 2>&1 | FileCheck
--check-prefix=NON-APX %s
+// RUN: %clang_cl -### --targe
https://github.com/fzou1 updated
https://github.com/llvm/llvm-project/pull/140874
>From d683302d4768dfb5c618aa1b09553f3b22142aed Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Tue, 20 May 2025 22:10:07 +0800
Subject: [PATCH 1/4] [Driver][X86] Add -m[no-]apxf to m_x86_Features_Group
This is to e
@@ -135,3 +135,53 @@
void f(void) {
}
+
+
+// RUN: not %clang_cl -### --target=i386 -mapx-features=ndd %s 2>&1 |
FileCheck --check-prefix=NON-APX %s
+// RUN: not %clang_cl -### --target=i386 -mapxf %s 2>&1 | FileCheck
--check-prefix=NON-APX %s
+// RUN: %clang_cl -### --targe
@@ -135,3 +135,53 @@
void f(void) {
}
+
+
+// RUN: not %clang_cl -### --target=i386 -mapx-features=ndd %s 2>&1 |
FileCheck --check-prefix=NON-APX %s
+// RUN: not %clang_cl -### --target=i386 -mapxf %s 2>&1 | FileCheck
--check-prefix=NON-APX %s
+// RUN: %clang_cl -### --targe
https://github.com/fzou1 updated
https://github.com/llvm/llvm-project/pull/140874
>From d683302d4768dfb5c618aa1b09553f3b22142aed Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Tue, 20 May 2025 22:10:07 +0800
Subject: [PATCH 1/3] [Driver][X86] Add -m[no-]apxf to m_x86_Features_Group
This is to e
@@ -6679,8 +6679,13 @@ def mapx_features_EQ : CommaJoined<["-"],
"mapx-features=">, Group,
Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">, Visibility<[ClangOption,
CLOption, FlangOption]>;
def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
HelpTex
https://github.com/fzou1 updated
https://github.com/llvm/llvm-project/pull/140874
>From d683302d4768dfb5c618aa1b09553f3b22142aed Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Tue, 20 May 2025 22:10:07 +0800
Subject: [PATCH 1/2] [Driver][X86] Add -m[no-]apxf to m_x86_Features_Group
This is to e
https://github.com/fzou1 created
https://github.com/llvm/llvm-project/pull/140874
This is to expose these options to clang-cl on Windows. And add help text for
these options.
>From d683302d4768dfb5c618aa1b09553f3b22142aed Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Tue, 20 May 2025 22:10:07
fzou1 wrote:
> We should avoid introducing a new cmake config for changes like this. You
> could utilize clang config file to specify the option.
>
> lld change should have been separated
Sorry for late reply. The related cmake and LLD changes were reverted. Only a
backend pass and option wer
fzou1 wrote:
Sorry. The test failure had been fixed in
https://github.com/llvm/llvm-project/pull/137794.
https://github.com/llvm/llvm-project/pull/136660
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@@ -1257,6 +1259,26 @@ inline bool isX86_64ExtendedReg(MCRegister Reg) {
return false;
}
+inline const TargetRegisterClass *
+constrainRegClassToNonRex2(const TargetRegisterClass *RC) {
fzou1 wrote:
I wrote it based on canUseApxExtendedReg function. Updated
@@ -0,0 +1,236 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
fzou1 wrote:
> > > > Suppress EGPR/NDD instructions for relocations to avoid APX relocation
> > > > types emitted. This is to keep backward compatibility with old version
> > > > of ld and other linkers without APX support. If there are APX
> > > > relocation types, old version of linkers woul
https://github.com/fzou1 edited https://github.com/llvm/llvm-project/pull/136660
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fzou1 wrote:
> > Suppress EGPR/NDD instructions for relocations to avoid APX relocation
> > types emitted. This is to keep backward compatibility with old version of
> > ld and other linkers without APX support. If there are APX relocation
> > types, old version of linkers would raise "unsuppo
fzou1 wrote:
> > > Any comments?
> >
> >
> > Still not understand the requirement...
>
> I'm confused by the test cases too. I understood the code as we replace the
> EGPR or NDD instructions with non-APX ones, which meets my expection. But the
> option and tests are in MC phase, which means
fzou1 wrote:
> > Any comments?
>
> Still not understand the requirement...
I've update commit message with an example. Please take a look.
https://github.com/llvm/llvm-project/pull/136660
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@@ -0,0 +1,173 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -89,6 +89,7 @@ set(sources
GISel/X86InstructionSelector.cpp
GISel/X86LegalizerInfo.cpp
GISel/X86RegisterBankInfo.cpp
+ X86SuppressAPXForReloc.cpp
fzou1 wrote:
Will do
https://github.com/llvm/llvm-project/pull/136660
_
https://github.com/fzou1 deleted
https://github.com/llvm/llvm-project/pull/136660
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@@ -912,9 +912,9 @@ void X86_64::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_X86_64_CODE_4_GOTPC32_TLSDESC:
case R_X86_64_TLSDESC_CALL:
case R_X86_64_TLSGD:
-if (rel.expr == R_RELAX_TLS_GD_TO_LE) {
+if (rel.expr == R_RELAX_TLS_GD_TO
@@ -912,9 +912,9 @@ void X86_64::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_X86_64_CODE_4_GOTPC32_TLSDESC:
case R_X86_64_TLSDESC_CALL:
case R_X86_64_TLSGD:
-if (rel.expr == R_RELAX_TLS_GD_TO_LE) {
+if (rel.expr == R_RELAX_TLS_GD_TO
@@ -89,6 +89,7 @@ set(sources
GISel/X86InstructionSelector.cpp
GISel/X86LegalizerInfo.cpp
GISel/X86RegisterBankInfo.cpp
+ X86SuppressAPXForReloc.cpp
fzou1 wrote:
Will do
https://github.com/llvm/llvm-project/pull/136660
_
@@ -0,0 +1,173 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -1,44 +1,84 @@
// REQUIRES: x86
-// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
+// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
-x86-apx-relax-relocations=true
// RUN: ld.lld %t.o -o %t1
// RUN: llvm-readobj -r %t1 | FileCheck -
fzou1 wrote:
Any comments?
https://github.com/llvm/llvm-project/pull/136660
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https://github.com/fzou1 updated
https://github.com/llvm/llvm-project/pull/136660
>From a98371ac23728289b7e1b9a1516141158bf7c1e0 Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Tue, 22 Apr 2025 11:05:29 +0800
Subject: [PATCH 1/3] [X86] Implement disabling APX relocations and EPGR/NDD
instrs for
fzou1 wrote:
> > > > Introduce an option (-mapx-relax-relocations) to control the emission
> > > > of the new APX relocations. It's off by default to keep backward
> > > > compatibility with old version of ld and other linkers without APX
> > > > support. And EGPR and NDD are also suppressed t
https://github.com/fzou1 updated
https://github.com/llvm/llvm-project/pull/136660
>From a98371ac23728289b7e1b9a1516141158bf7c1e0 Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Tue, 22 Apr 2025 11:05:29 +0800
Subject: [PATCH 1/2] [X86] Implement disabling APX relocations and EPGR/NDD
instrs for
fzou1 wrote:
> > Introduce an option (-mapx-relax-relocations) to control the emission of
> > the new APX relocations. It's off by default to keep backward compatibility
> > with old version of ld and other linkers without APX support. And EGPR and
> > NDD are also suppressed to avoid the inst
https://github.com/fzou1 created
https://github.com/llvm/llvm-project/pull/136660
Introduce an option (-mapx-relax-relocations) to control the emission of the
new APX relocations. It's off by default to keep backward compatibility with
old version of ld and other linkers without APX support. A
https://github.com/fzou1 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/123270
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https://github.com/fzou1 updated
https://github.com/llvm/llvm-project/pull/116737
>From c1716f030d8503b5a4742447ef8883d900521c34 Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Tue, 19 Nov 2024 11:19:17 +0800
Subject: [PATCH 1/2] [X86][MC,LLD][NFC] Rename R_X86_64_REX2_GOTPCRELX to
R_X86_64_CODE
https://github.com/fzou1 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/115660
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@@ -0,0 +1,301 @@
+/*===- amxcomplextransposeintrin.h - AMX-COMPLEX and AMX-TRANSPOSE
--===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,94 @@
+/*===- amxbf16transposeintrin.h - AMX-BF16 and AMX-TRANSPOSE
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apa
@@ -0,0 +1,301 @@
+/*===- amxcomplextransposeintrin.h - AMX-COMPLEX and AMX-TRANSPOSE
--===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,94 @@
+/*===- amxfp16transposeintrin.h - AMX-FP16 and AMX-TRANSPOSE
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apa
@@ -0,0 +1,301 @@
+/*===- amxcomplextransposeintrin.h - AMX-COMPLEX and AMX-TRANSPOSE
--===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,301 @@
+/*===- amxcomplextransposeintrin.h - AMX-COMPLEX and AMX-TRANSPOSE
--===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -275,6 +276,27 @@ std::pair
ShapeCalculator::getShape(IntrinsicInst *II,
Col = II->getArgOperand(1);
break;
}
+ case Intrinsic::x86_ttdpbf16ps_internal:
+ case Intrinsic::x86_ttdpfp16ps_internal:
+ case Intrinsic::x86_ttcmmimfp16ps_internal:
+ case Intrinsic::
fzou1 wrote:
> Missing IR test?
Sorry. Added. Thanks.
https://github.com/llvm/llvm-project/pull/115829
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@@ -15,81 +15,214 @@
#define __AMXFP8INTRIN_H
#ifdef __x86_64__
-/// Peform the dot product of a BF8 value \a a by a BF8 value \a b accumulating
-/// into a Single Precision (FP32) source/dest \a dst.
+#define __DEFAULT_FN_ATTRS_FP8
https://github.com/fzou1 updated
https://github.com/llvm/llvm-project/pull/115829
>From 9fd6e9e598423b6cc58a25fe70cc12a846483be5 Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Thu, 7 Nov 2024 11:56:17 +0800
Subject: [PATCH 1/2] [X86][AMX] Add AMX FP8 new APIs
This is a follow-up to #113850.
Re
https://github.com/fzou1 created
https://github.com/llvm/llvm-project/pull/115829
This is a follow-up to #113850.
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
>From 9fd6e9e598423b6cc58a25fe70cc12a846483be5 Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Thu, 7 Nov 2024 11:56:17 +0800
@@ -6101,6 +6101,25 @@ let TargetPrefix = "x86" in {
Intrinsic<[llvm_v16i32_ty],
[llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty,
llvm_i32_ty],
[]>;
+
+ def int_x86_tmmultf32ps : ClangBuiltin<"__builtin_ia32_tmmultf32ps"
@@ -660,6 +660,10 @@ _storebe_i64(void * __P, long long __D) {
#include
#endif
+#if !defined(__SCE__) || __has_feature(modules) || defined(__AMX_TF32__)
+#include
+#endif
+
fzou1 wrote:
Added.
https://github.com/llvm/llvm-project/pull/115625
__
@@ -151,6 +151,7 @@ set(x86_files
amxfp16intrin.h
amxfp8intrin.h
amxintrin.h
+ amxtf32intrin.h
fzou1 wrote:
Sorry. Forgot to add it. Done. Thanks.
https://github.com/llvm/llvm-project/pull/115625
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https://github.com/llvm/llvm-project/pull/115625
>From b1d9799b99b45b5af2b63868c4c3b139dbf9378c Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Sat, 26 Oct 2024 18:44:32 +0800
Subject: [PATCH 1/4] [X86][AMX] Support AMX-TF32
Ref.: https://cdrdv2.intel.com/v1/dl/g
https://github.com/fzou1 updated
https://github.com/llvm/llvm-project/pull/115625
>From b1d9799b99b45b5af2b63868c4c3b139dbf9378c Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Sat, 26 Oct 2024 18:44:32 +0800
Subject: [PATCH 1/3] [X86][AMX] Support AMX-TF32
Ref.: https://cdrdv2.intel.com/v1/dl/g
https://github.com/fzou1 updated
https://github.com/llvm/llvm-project/pull/115625
>From b1d9799b99b45b5af2b63868c4c3b139dbf9378c Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Sat, 26 Oct 2024 18:44:32 +0800
Subject: [PATCH 1/2] [X86][AMX] Support AMX-TF32
Ref.: https://cdrdv2.intel.com/v1/dl/g
https://github.com/fzou1 created
https://github.com/llvm/llvm-project/pull/115625
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368
>From b1d9799b99b45b5af2b63868c4c3b139dbf9378c Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Sat, 26 Oct 2024 18:44:32 +0800
Subject: [PATCH] [X86][AMX] Supp
https://github.com/fzou1 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/114070
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@@ -369,3 +369,150 @@ let Predicates = [HasAMXTRANSPOSE, In64BitMode] in {
}
}
} // HasAMXTILE, HasAMXTRANSPOSE
+
+multiclass m_tcvtrowd2ps {
+ let Predicates = [HasAMXAVX512, In64BitMode] in {
fzou1 wrote:
Should add HasAVX10_2_512 in line 374, 390 and
https://github.com/fzou1 edited https://github.com/llvm/llvm-project/pull/114070
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https://github.com/fzou1 commented:
LGTM except the last place probably missing avx10.2-512 dependency.
https://github.com/llvm/llvm-project/pull/114070
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@@ -0,0 +1,381 @@
+/*===- amxavx512intrin.h - AMXAVX512
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -133,6 +133,12 @@ TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz0t1_internal,
"vUsUsUsV256i*V256i*vC*z",
TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz1_internal, "vUsUsUsV256i*V256i*vC*z",
"n", "amx-transpose")
TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz1t1_internal,
"vUsUsUsV256i*V256i
@@ -133,6 +133,12 @@ TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz0t1_internal,
"vUsUsUsV256i*V256i*vC*z",
TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz1_internal, "vUsUsUsV256i*V256i*vC*z",
"n", "amx-transpose")
TARGET_BUILTIN(__builtin_ia32_t2rpntlvwz1t1_internal,
"vUsUsUsV256i*V256i
@@ -0,0 +1,381 @@
+/*===- amxavx512intrin.h - AMXAVX512
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,381 @@
+/*===- amxavx512intrin.h - AMXAVX512
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -0,0 +1,381 @@
+/*===- amxavx512intrin.h - AMXAVX512
===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -559,12 +559,68 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
return true;
}
case X86::PTILELOADDV:
- case X86::PTILELOADDT1V: {
+ case X86::PTILELOADDT1V:
+ case X86::PTCVTROWD2PSrreV:
+ case X86::PTCVTROWD2PSrriV:
+ case X86::PTCVTROWPS2PBF16HrreV:
https://github.com/fzou1 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/113532
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https://github.com/fzou1 deleted
https://github.com/llvm/llvm-project/pull/113532
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@@ -0,0 +1,248 @@
+/* ===--- amxtransposeintrin.h - AMX_TRANSPOSE intrinsics -*- C++
-*-===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -34,9 +34,31 @@ class ShapeT {
if (MRI)
deduceImm(MRI);
}
+ // When ShapeT has mult shapes, we only use Shapes (never use Row and Col)
+ // and ImmShapes. Due to the most case is only one shape (just simply use
+ // Shape.Row or Shape.Col), so here we don't me
@@ -623,6 +623,37 @@ struct X86Operand final : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createReg(Reg));
}
+ bool isTILEPair() const {
+return Kind == Register &&
+ X86MCRegisterClasses[X86::TILERegClassID].contains(getReg());
---
@@ -0,0 +1,248 @@
+/* ===--- amxtransposeintrin.h - AMX_TRANSPOSE intrinsics -*- C++
-*-===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -919,23 +1017,66 @@ bool X86LowerAMXCast::optimizeAMXCastFromPhi(
return true;
}
+static Value *getShapeFromAMXIntrinsic(Value *Inst, unsigned ShapeIdx,
+ bool IsRow) {
+ if (!isAMXIntrinsic(Inst))
+return nullptr;
+
+ auto *II
@@ -34,9 +34,31 @@ class ShapeT {
if (MRI)
deduceImm(MRI);
}
+ // When ShapeT has mult shapes, we only use Shapes (never use Row and Col)
fzou1 wrote:
mult -> multiple
https://github.com/llvm/llvm-project/pull/113532
_
@@ -121,12 +137,96 @@ static Instruction
*getFirstNonAllocaInTheEntryBlock(Function &F) {
llvm_unreachable("No terminator in the entry block!");
}
-static std::pair getShape(IntrinsicInst *II, unsigned OpNo) {
+class ShapeCalculator {
+private:
+ TargetMachine *TM = nullpt
@@ -16920,6 +16920,58 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned
BuiltinID,
// instruction, but it will create a memset that won't be optimized away.
return Builder.CreateMemSet(Ops[0], Ops[1], Ops[2], Align(1), true);
}
+ // Corresponding to intrisics w
@@ -0,0 +1,248 @@
+/* ===--- amxtransposeintrin.h - AMX_TRANSPOSE intrinsics -*- C++
-*-===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Ap
@@ -80,28 +80,41 @@ INITIALIZE_PASS_BEGIN(X86FastTileConfig, DEBUG_TYPE,
INITIALIZE_PASS_END(X86FastTileConfig, DEBUG_TYPE,
"Fast Tile Register Configure", false, false)
-static bool isTileDef(MachineRegisterInfo *MRI, MachineInstr &MI) {
+static unsigned g
@@ -0,0 +1,83 @@
+/*===- amxfp8intrin.h - AMX intrinsics -*- C++
-*===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apa
https://github.com/fzou1 updated
https://github.com/llvm/llvm-project/pull/113850
>From fd570cb8d41f5f94b61d515985245fc81aab633e Mon Sep 17 00:00:00 2001
From: Feng Zou
Date: Thu, 24 Oct 2024 21:56:48 +0800
Subject: [PATCH 1/5] Support AMX-FP8
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/67
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