quic-garvgupt wrote:
Fix for tests failing on https://lab.llvm.org/buildbot/#/builders/11 -
https://github.com/llvm/llvm-project/pull/144655
https://github.com/llvm/llvm-project/pull/144640
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https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/144655
Fuchsia sets CLANG_DEFAULT_UNWINDLIB to libunwind. As a result, when rtlib is
set to libgcc and unwindlib is not explicitly specified, tests using Fuchsia as
the default platform will fail. To address thi
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/144649
This patch conditionalise the addition of crt{begin,end}.o object files
along with addition of -lgloss lib based on whether libc selected is newlib or
llvm libc. Since there is no way a user can specify whi
https://github.com/quic-garvgupt closed
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quic-garvgupt wrote:
> > Do the fuchsia builders actually produce output on a failure? We seem to
> > just get exit code 1, but no indication of what filecheck had problems with.
>
> They do; here's a link! Let me know if you have an problems with the Web UI;
> I can paste things here if so.
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/144640
This patch introduces enhancements to the Baremetal toolchain to support
GCC toolchain detection.
- If the --gcc-install-dir or --gcc-toolchain options are provided and
point to valid paths, the sysroot is
quic-garvgupt wrote:
> `ToolChain::UnwindLibType ToolChain::GetUnwindLibType( const ArgList &Args)
> const { if (unwindLibType) return *unwindLibType;
>
> const Arg *A = Args.getLastArg(options::OPT_unwindlib_EQ); StringRef LibName
> = A ? A->getValue() : CLANG_DEFAULT_UNWINDLIB;`
>
> If --un
quic-garvgupt wrote:
`ToolChain::UnwindLibType ToolChain::GetUnwindLibType(
const ArgList &Args) const {
if (unwindLibType)
return *unwindLibType;
const Arg *A = Args.getLastArg(options::OPT_unwindlib_EQ);
StringRef LibName = A ? A->getValue() : CLANG_DEFAULT_UNWINDLIB;`
I
quic-garvgupt wrote:
`ToolChain::UnwindLibType ToolChain::GetUnwindLibType(
const ArgList &Args) const {
if (unwindLibType)
return *unwindLibType;
const Arg *A = Args.getLastArg(options::OPT_unwindlib_EQ);
StringRef LibName = A ? A->getValue() : CLANG_DEFAULT_UNWINDLIB;`
If the
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132808
>From f4a5757a8abf6ff7ba3e064533f3993a0ed0198e Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 07:04:59 -0700
Subject: [PATCH] [Driver] Forward sysroot from Driver to linker in BareMetal
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/132808
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https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132807
>From 7f26ac995e18f71ec8bccdb5b39be95bf629da19 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 06:49:09 -0700
Subject: [PATCH] [Driver] Add option to force udnefined symbols during linki
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/132807
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https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/132806
>From fa8aad1e9df9b21696fea33de4678a809a13367c Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 06:17:42 -0700
Subject: [PATCH] [Driver] Fix link order of BareMetal toolchain object
The
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/132806
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https://github.com/llvm/llvm-project/pull/121830
>From c490d1f4f1d1c3a65ad722d46b87fe49ade11c21 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 24 Mar 2025 04:58:57 -0700
Subject: [PATCH] [Driver] Add support for crtbegin.o, crtend.o and libgloss
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/121830
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quic-garvgupt wrote:
Gentle Ping!
https://github.com/llvm/llvm-project/pull/143692
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@@ -110,56 +145,113 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
-BareMetal::BareMetal(const Driver &D, const llvm::Triple &Triple,
- const ArgList &Args)
-: ToolChain(D, Triple, Ar
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121829
>From f19e2e0abc5e6ad2144772cb654e7b86d28f0efd Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [Driver] Teach Barmetal toolchain about GCC installation
T
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/143692
>From e4902f765b0ef58e015195f2b4974d1f44c6b0c1 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 26 May 2025 10:45:37 -0700
Subject: [PATCH] Pass TargetMachine from from Clang to `BitcodeWriter`and
`
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/143692
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quic-garvgupt wrote:
@smithp35 , could you pls parallely also review PR -
https://github.com/llvm/llvm-project/pull/121831? I added you as reviewer there
as well in the beginning and will appreciate your comments/feedback. Thanks!
https://github.com/llvm/llvm-project/pull/121829
__
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/121829
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quic-garvgupt wrote:
Hi @petrhosek, while petrsmith is reviewing this PR, if you don’t have any
further suggestions, comments, or feedback, could you please provide an LGTM?
That would help us proceed with merging the PR promptly once petr approves it.
Thanks so much!
https://github.com/llvm/
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121829
>From c4d61f3eafe108d705a67a9b8b7ca640119afe78 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [Driver] Teach Barmetal toolchain about GCC installation
T
@@ -110,56 +144,99 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
-BareMetal::BareMetal(const Driver &D, const llvm::Triple &Triple,
- const ArgList &Args)
-: ToolChain(D, Triple, Arg
@@ -110,56 +144,99 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
-BareMetal::BareMetal(const Driver &D, const llvm::Triple &Triple,
- const ArgList &Args)
-: ToolChain(D, Triple, Arg
quic-garvgupt wrote:
> I've done another review pass. Mostly some small stylistic comments.
>
> I'm finding it difficult to follow the code with the various different
> code-paths with similar names. I've made some suggestions on renaming. We may
> also be able to add some more comments to mak
@@ -110,56 +144,99 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
-BareMetal::BareMetal(const Driver &D, const llvm::Triple &Triple,
- const ArgList &Args)
-: ToolChain(D, Triple, Arg
@@ -110,56 +144,99 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
-BareMetal::BareMetal(const Driver &D, const llvm::Triple &Triple,
- const ArgList &Args)
-: ToolChain(D, Triple, Arg
@@ -110,56 +144,99 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
-BareMetal::BareMetal(const Driver &D, const llvm::Triple &Triple,
- const ArgList &Args)
-: ToolChain(D, Triple, Arg
@@ -110,56 +144,99 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
-BareMetal::BareMetal(const Driver &D, const llvm::Triple &Triple,
- const ArgList &Args)
-: ToolChain(D, Triple, Arg
@@ -110,20 +110,81 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+static bool hasGCCToolChainAlongSideClang(const Driver &D) {
+ SmallString<128> GCCDir;
+ llvm::sys::path::append(GCCDir, D.Dir, "..", D.g
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121829
>From 0ffc48d7367a37a9a02333456a9dbfc20ab9e71f Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [Driver] Teach Barmetal toolchain about GCC installation
T
quic-garvgupt wrote:
Hi @smithp35, can you pls review the latest changes and approve this PR if
everything looks fine?
https://github.com/llvm/llvm-project/pull/121829
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https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121829
>From 63eaf99ffe04d8c66bf11ec3bad6b04b83de3c96 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [Driver] Teach Barmetal toolchain about GCC installation
T
@@ -110,20 +110,81 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+static bool hasGCCToolChainAlongSideClang(const Driver &D) {
+ SmallString<128> GCCDir;
+ llvm::sys::path::append(GCCDir, D.Dir, "..", D.g
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121829
>From 8d6d2e0f1eaa0b81613a786dbe003ddf7d0a2983 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [Driver] Teach Barmetal toolchain about GCC installation
T
@@ -110,20 +110,81 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+static bool hasGCCToolChainAlongSideClang(const Driver &D) {
+ SmallString<128> GCCDir;
+ llvm::sys::path::append(GCCDir, D.Dir, "..", D.g
@@ -110,20 +110,81 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+static bool hasGCCToolChainAlongSideClang(const Driver &D) {
+ SmallString<128> GCCDir;
+ llvm::sys::path::append(GCCDir, D.Dir, "..", D.g
quic-garvgupt wrote:
> I'm looking at this patch in isolation, so its possible that the comments
> here are addressed elasewhere.
>
> It looks like useful functionality to add to the bare metal driver.
>
> It also looks like there is some scope for some documentation, for users and
> for tool
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121829
>From 1d0db96afab52903a267d600cab02c24900101af Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [Driver] Teach Barmetal toolchain about GCC installation
T
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/121829
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quic-garvgupt wrote:
Hi @petrhosek, I've addressed all your comments. Please review the changes and
approve the PR if everything looks good.
https://github.com/llvm/llvm-project/pull/121829
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@@ -79,7 +87,6 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
OrderedMultilibs getOrderedMultilibs() const;
std::string SysRoot;
quic-garvgupt wrote:
Removing this private variable was making the code messy because there have
been update
@@ -110,20 +110,76 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+std::string BareMetal::computeSysRoot() const {
+ if (!SysRoot.empty())
+return SysRoot;
+
+ std::string SysRoot = getDriver().SysRoot
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/121829
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https://github.com/llvm/llvm-project/pull/121829
>From e07a4cd4e0ff77f74b66695923bc998904c14746 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [Driver] Teach Barmetal toolchain about GCC installation
T
quic-garvgupt wrote:
Hi @petrhosek, I've addressed all your comments. Please review the changes and
approve the PR if everything looks good.
https://github.com/llvm/llvm-project/pull/121829
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>From 9bb78235d2ba008dc49dc4746edbd9978a92396b Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [RISCV] Teach Barmetal toolchain about GCC installation(1/3
@@ -110,20 +111,93 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+// GCC sysroot here means form sysroot from either --gcc-install-dir, or from
+// --gcc-toolchain or if the toolchain is installed alongside
quic-garvgupt wrote:
It's been a few weeks since this patch was last reviewed. If everything looks
good, could someone please provide an LGTM? I'd like to merge this patch soon.
https://github.com/llvm/llvm-project/pull/121829
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quic-garvgupt wrote:
Hi @petrhosek, following up on our last RISC-V embedded sync-up, can you please
review this patch? Thanks
https://github.com/llvm/llvm-project/pull/121829
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quic-garvgupt wrote:
Gentle Ping again!
https://github.com/llvm/llvm-project/pull/121829
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@@ -110,20 +111,93 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+// GCC sysroot here means form sysroot from either --gcc-install-dir, or from
+// --gcc-toolchain or if the toolchain is installed alongside
quic-garvgupt wrote:
Gentle Ping!
https://github.com/llvm/llvm-project/pull/121829
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https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/121829
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quic-garvgupt wrote:
I have divided this PR into three separate PRs to streamline the review process
and ensured that ARM and RISCV tests are not modified in the same PR. Please
review them and provide any feedback or comments. Thanks!
[RISCV] Teach Barmetal toolchain about GCC installation(1/
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121829
>From 03b91a8d408bacec17391b995611dbbb0ea62edd Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [RISCV] Teach Barmetal toolchain about GCC installation(1/3
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121829
>From 02d70a2c1fa746eafa87308f0c8109bb2c91164f Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Fri, 13 Dec 2024 05:31:56 -0800
Subject: [PATCH] [RISCV] Teach Barmetal toolchain about GCC installation(1/3
https://github.com/quic-garvgupt edited
https://github.com/llvm/llvm-project/pull/121829
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https://github.com/quic-garvgupt ready_for_review
https://github.com/llvm/llvm-project/pull/121829
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quic-garvgupt wrote:
* **#121829** https://app.graphite.dev/github/pr/llvm/llvm-project/121829?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-projec
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/121829
This patch introduces the baretmetal toolchain object about GCC Installation.
Currently, if `--gcc-installation` ot `--gcc-install-dir` options are passed on
commandline, then sysroot will be formed from th
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/121821
This patch introduces the baretmetal toolchain object about GCC Installation.
Currently, if `--gcc-installation` ot `--gcc-install-dir` options are passed on
commandline, then sysroot will be formed from
https://github.com/quic-garvgupt closed
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@@ -78,8 +86,9 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
using OrderedMultilibs =
llvm::iterator_range::const_reverse_iterator>;
OrderedMultilibs getOrderedMultilibs() const;
-
+ bool UseLD;
quic-garvgupt wrote:
please see my
@@ -110,20 +111,95 @@ static std::string computeBaseSysRoot(const Driver &D,
bool IncludeTriple) {
return std::string(SysRootDir);
}
+// GCC sysroot here means form sysroot from either --gcc-install-dir, or from
+// --gcc-toolchain or if the toolchain is installed alongside
@@ -6521,11 +6521,7 @@ const ToolChain &Driver::getToolChain(const ArgList
&Args,
break;
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
-if (toolchains::RISCVToolChain::hasGCCToolchain(*this, Args))
- TC =
- std::make_
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/118809
>From b58f9dd197c78b1e39676022a421ca0e6d5552a5 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 13 Nov 2024 02:45:51 -0800
Subject: [PATCH] [WIP] Merging RISCVToolChain and BareMetal toolchains
Curr
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/118809
>From 569feb86c654be044781aa5968907a72ea882e88 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 13 Nov 2024 02:45:51 -0800
Subject: [PATCH] [WIP] Merging RISCVToolChain and BareMetal toolchains
Curr
@@ -503,12 +624,22 @@ void baremetal::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
const llvm::Triple::ArchType Arch = TC.getArch();
const llvm::Triple &Triple = getToolChain().getEffectiveTriple();
- AddLinkerInputs(TC, Inputs, Args, CmdArgs, JA);
+ if (!D
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/118809
>From b74795d44846b79252bd3fb1f1e8179311725c74 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 13 Nov 2024 02:45:51 -0800
Subject: [PATCH] [RISCV] Merging RISCVToolChain and BareMetal toolchains
Cu
https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/118809
Currently, LLVM has two RISC-V toolchain classes in Clang for baremetal
development, creating unnecessary maintenance overhead. This patch extends the
BareMetal toolchain to support an existing GCC instal
quic-garvgupt wrote:
I believe the patch is ready to be merged now, but since I am not the reviewer
here, someone else must approve it as well.
Thanks again for the patch!
https://github.com/llvm/llvm-project/pull/83896
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quic-garvgupt wrote:
Thanks for the prompt reply and latest patchset.
1. Do we need to add documentation in RISCVUsage.rst file for xsfcease?
2. Also, as we are adding cease instruction in this PR, can we rename the PR to
include the cease instruction as well?
https://github.com/llvm/llvm-proj
quic-garvgupt wrote:
Thanks for clearing the confusion around whether rs1 would be optional or not.
Can we also add lit tests for the aliases?
https://github.com/llvm/llvm-project/pull/83896
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htt
quic-garvgupt wrote:
> > Also, I think we might need to update the extensions in the
> > `RISCVProcessors.td` file under SIFIVE_S76 microcontroller?
>
> This is a M-mode only extension, and we haven't historically been adding M or
> S mode extensions to the -mcpu lists. Except for `xiangshan-n
quic-garvgupt wrote:
> > Hi @topperc, can you add instruction alias for cflush and cdiscard
> > instructions when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1`
> > respectively, as this register is optional according to spec?
>
> x0 has special meaning, but the spec never says it is "
quic-garvgupt wrote:
Also, I think we might need to update the extensions in the
`RISCVProcessors.td` file under SIFIVE_S76 microcontroller?
https://github.com/llvm/llvm-project/pull/83896
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quic-garvgupt wrote:
Hi @topperc, can you add instruction alias for cflush and cdiscard instructions
when the rs1 is X0 to `sf.cflush.d.l1` and `sf.cflush.d.l1` respectively, as
this register is optional according to spec?
https://github.com/llvm/llvm-project/pull/83896
_
quic-garvgupt wrote:
ping! for merging this PR
https://github.com/llvm/llvm-project/pull/81727
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quic-garvgupt wrote:
Hi @MaskRay, please review the updated changes and if they are fine, please
merge this PR on my behalf. Thanks!
https://github.com/llvm/llvm-project/pull/81727
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https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/81727
>From 0d1f9be389a41ba2f1531bf13e8d1f14aadf9eeb Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 14 Feb 2024 03:00:20 -0800
Subject: [PATCH] [RISCV] Disable generation of asynchronous unwind tables for
quic-garvgupt wrote:
Hi @asb, I do not have write access, requesting to merge this PR on my behalf.
Also, requesting to backport this PR onto the release branch. Thanks in
advance!
https://github.com/llvm/llvm-project/pull/81727
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@@ -421,3 +421,11 @@
// MIPSN32R6EL: "-target-cpu" "mips64r6"
// MIPSN32R6EL: "-target-abi" "n32"
// MIPSN32R6EL: "-mfloat-abi" "hard"
+
+// RUN: %clang --target=riscv32-unknown-elf --gcc-toolchain="" -### %s 2>&1 |
FileCheck %s -check-prefix=NOUWTABLE
quic-ga
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/81727
>From 8cc7535ed4c05d4cf14cdedc26077eccf06c8d53 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 14 Feb 2024 03:00:20 -0800
Subject: [PATCH] [RISCV] Disable generation of asynchronous unwind tables for
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/81727
>From 42211bccd8ffc60751234ab5695be135ea8b6373 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 14 Feb 2024 03:00:20 -0800
Subject: [PATCH] [RISCV] Disable generation of asynchronous unwind tables for
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/81727
>From 42211bccd8ffc60751234ab5695be135ea8b6373 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Wed, 14 Feb 2024 03:00:20 -0800
Subject: [PATCH 1/2] [RISCV] Disable generation of asynchronous unwind tables
quic-garvgupt wrote:
Hi @asb, since Petr already gave a good-ahead to this patch in the meeting, let
me know if we can merge this PR if there are no new changes need to be made
https://github.com/llvm/llvm-project/pull/81727
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quic-garvgupt wrote:
Hi
@jonathonpenix @apazos @kito-cheng @asb @MaskRay - Requesting for adding as
reviewers to review the PR. Thanks in advance!
https://github.com/llvm/llvm-project/pull/81727
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https://github.com/quic-garvgupt created
https://github.com/llvm/llvm-project/pull/81727
The below culprit patch enabled the generation of asynchronous unwind tables
(-funwind-tables=2) by default for RISCV for both linux and RISCVToolChain
baremetal object. However, since there are 2 baremeta
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