[clang] [llvm] [RISCV] Remove experimental for bf16 extensions (PR #97996)

@@ -271,7 +271,7 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zalasr`` LLVM implements the `0.0.5 draft specification `__. -``experimental-zfbfmin``,

[clang] [lld] [llvm] [RISCV] Make M imply Zmmul (PR #95070)

https://github.com/jacquesguan closed https://github.com/llvm/llvm-project/pull/95070 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [lld] [llvm] [RISCV] Make M imply Zmmul (PR #95070)

jacquesguan wrote: > We intentionally didn't do this because it makes LLVM not work with binutils > that doesn't know about Zmmul. Maybe enough time has passed that it is no > longer an issue? Since Zmmul was ratified at june 2022, I think it's OK to update it now.

[clang] [lld] [llvm] [RISCV] Make M imply Zmmul (PR #95070)

https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/95070 >From dfbbcec9140f625309f78ca98c45b26b89fb71b1 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Thu, 6 Jun 2024 14:21:12 +0800 Subject: [PATCH] [RISCV] Make M imply Zmmul According to the spec, M implies

[clang] [llvm] [RISCV] Make M imply Zmmul (PR #95070)

https://github.com/jacquesguan created https://github.com/llvm/llvm-project/pull/95070 According to the spec, M implies Zmmul. >From b68778d7b46d3f0fd287c5e215ac0f794244604c Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Thu, 6 Jun 2024 14:21:12 +0800 Subject: [PATCH] [RISCV] Make M imply

[clang] [clang][AVR] Restrict range of assembly constraint 'G' (PR #76561)

https://github.com/jacquesguan approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76561 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

https://github.com/jacquesguan closed https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

jacquesguan wrote: > > > I think the conclusion from the LLVM sync-up call was that everyone happy > > > to move in this direction, so please add the release note and we can do a > > > final review. Thanks! > > > > > > Done, added release note. > > > > Thanks! Sorry I wasn't specific

[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From 4e5442531d5412e83399eb918ba405dcd580b227 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi with f extension but

[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

jacquesguan wrote: > I think the conclusion from the LLVM sync-up call was that everyone happy to > move in this direction, so please add the release note and we can do a final > review. Thanks! Done, added release note. https://github.com/llvm/llvm-project/pull/73489

[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From dcc71641695128e117b290cd1e63879e0beeb796 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi with f extension but

[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

@@ -1,4 +1,4 @@ -// Check target CPUs are correctly passed. +·// Check target CPUs are correctly passed. jacquesguan wrote: Fixed https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list

[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

https://github.com/jacquesguan edited https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)

https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From ce22351f42b0a641000d1aa4db86f090f9b4e6c8 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi with f extension but

[llvm] [clang] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)

jacquesguan wrote: soft ping... Any more advice? https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)

https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From daaa69ada14be2b1c907acf961e3ceb4f355f927 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi when only have f extension

[llvm] [clang] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)

https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From e03da61c3ad76b76a99639ad1735ec556aaec10b Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi when only have f extension

[clang] [llvm] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)

https://github.com/jacquesguan created https://github.com/llvm/llvm-project/pull/73489 Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is different with riscv-gnu-toolchain. In

[clang] [RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (PR #73091)

https://github.com/jacquesguan closed https://github.com/llvm/llvm-project/pull/73091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (PR #73091)

jacquesguan wrote: > test? Done, add test case. https://github.com/llvm/llvm-project/pull/73091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (PR #73091)

https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73091 >From 5712baa1f74acec9a482d110e0a6bf9638006409 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Wed, 22 Nov 2023 14:34:49 +0800 Subject: [PATCH] [RISCV] Use Float type instead of Half type for Fixed RVV

[clang] [RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (PR #73091)

https://github.com/jacquesguan created https://github.com/llvm/llvm-project/pull/73091 None >From f785a0a175f509dbc72e11c13eb5eb6f6eaebb43 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Wed, 22 Nov 2023 14:34:49 +0800 Subject: [PATCH] [RISCV] Use Float type instead of Half type for Fixed

[clang] [clang][driver] Add avr-libc's default linker script to lld (PR #68507)

https://github.com/jacquesguan approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/68507 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Fix the condition of checking signature in getIndex (PR #67403)

https://github.com/jacquesguan closed https://github.com/llvm/llvm-project/pull/67403 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][driver] Support option '-r' for target AVR (PR #68484)

https://github.com/jacquesguan approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/68484 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Fix the condition of checking signature in getIndex (PR #67403)

https://github.com/jacquesguan created https://github.com/llvm/llvm-project/pull/67403 The current condition causes assert failing if try to add a new vendor vector file which only contains the same type signature. >From 3ad50442210c7303f0ac55339db778aa777532c8 Mon Sep 17 00:00:00 2001 From:

[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)

@@ -599,15 +599,21 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, def FeatureStdExtZvknha : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true", "'Zvknha' (Vector SHA-2 (SHA-256 only))">; - -def FeatureStdExtZvknhb

[clang] [RISCV] Add missing V extensions for zvk-invalid-features.c (PR #66875)

https://github.com/jacquesguan approved this pull request. https://github.com/llvm/llvm-project/pull/66875 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add missing V extensions for zvk-invalid-features.c (PR #66875)

jacquesguan wrote: LGTM https://github.com/llvm/llvm-project/pull/66875 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Update Zicntr and Zihpm to version 2p0 (PR #66323)

jacquesguan wrote: > Sorry, that was a mis-statement. There are two counter extensions you are > bumping. > > Anyway, rewording the commit message is a nit from me. OK, I retitle the commit. https://github.com/llvm/llvm-project/pull/66323 ___

[clang] [RISCV] Update counters to version 2p0 (PR #66323)

jacquesguan wrote: > Your commit bumps both the counter and timer extension, which makes your > commit message inaccurate. I think Counters in RISCV ISA include both "Zicntr" and "Zihpm", https://github.com/riscv/riscv-isa-manual/blob/main/src/counters.adoc.

[clang] 4d2536c - [RISCV] Enable more builtin for zvfhmin without zvfh

Author: Jianjian GUAN Date: 2023-09-08T10:55:17+08:00 New Revision: 4d2536c82fc426f0e622a09c0a3e048a0c734f3d URL: https://github.com/llvm/llvm-project/commit/4d2536c82fc426f0e622a09c0a3e048a0c734f3d DIFF: https://github.com/llvm/llvm-project/commit/4d2536c82fc426f0e622a09c0a3e048a0c734f3d.diff

[clang] 654fa9a - [RISCV] Add Zvfhmin extension for clang

Author: Jianjian GUAN Date: 2023-08-23T17:08:39+08:00 New Revision: 654fa9a7e898ce25a6d18f3a7c7b747e1059395b URL: https://github.com/llvm/llvm-project/commit/654fa9a7e898ce25a6d18f3a7c7b747e1059395b DIFF: https://github.com/llvm/llvm-project/commit/654fa9a7e898ce25a6d18f3a7c7b747e1059395b.diff

[clang] 28741a2 - [clang][SVE] Rename isVLSTBuiltinType, NFC

Author: Jianjian GUAN Date: 2023-08-17T14:18:32+08:00 New Revision: 28741a23c9fc5e9c9ba9cad8e71c3067544bcd66 URL: https://github.com/llvm/llvm-project/commit/28741a23c9fc5e9c9ba9cad8e71c3067544bcd66 DIFF: https://github.com/llvm/llvm-project/commit/28741a23c9fc5e9c9ba9cad8e71c3067544bcd66.diff

[clang] 9d0cf88 - [clang][doc] Mark _Float16 is support natively when Zfh or Zhinx is available

Author: Jianjian GUAN Date: 2023-08-14T11:27:15+08:00 New Revision: 9d0cf88e70860b29615253fbbd4d2d62eb08886a URL: https://github.com/llvm/llvm-project/commit/9d0cf88e70860b29615253fbbd4d2d62eb08886a DIFF: https://github.com/llvm/llvm-project/commit/9d0cf88e70860b29615253fbbd4d2d62eb08886a.diff

[clang] f808788 - [RISCV] Remove experimental for zihintntl

Author: Jianjian GUAN Date: 2023-08-10T17:04:49+08:00 New Revision: f808788487ab9db7da262a0b43483fb07bf6b50f URL: https://github.com/llvm/llvm-project/commit/f808788487ab9db7da262a0b43483fb07bf6b50f DIFF: https://github.com/llvm/llvm-project/commit/f808788487ab9db7da262a0b43483fb07bf6b50f.diff

[clang] 35a0079 - [RISCV] Add Zvfhmin extension for clang.

Author: Jianjian GUAN Date: 2023-05-31T14:31:11+08:00 New Revision: 35a0079238ce9fc36cdc8c6a2895eb5538bf7b4a URL: https://github.com/llvm/llvm-project/commit/35a0079238ce9fc36cdc8c6a2895eb5538bf7b4a DIFF: https://github.com/llvm/llvm-project/commit/35a0079238ce9fc36cdc8c6a2895eb5538bf7b4a.diff

[clang] 8e3a5a9 - [Driver][NFC] Simplify code.

Author: Jianjian GUAN Date: 2023-04-23T10:56:27+08:00 New Revision: 8e3a5a965a14f3d40c0ef07456e244509358abd7 URL: https://github.com/llvm/llvm-project/commit/8e3a5a965a14f3d40c0ef07456e244509358abd7 DIFF: https://github.com/llvm/llvm-project/commit/8e3a5a965a14f3d40c0ef07456e244509358abd7.diff