[clang] [AMDGPU][GFX12] Add tests for unsupported builtins (PR #78729)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/78729 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AMDGPU][GFX12] Add tests for unsupported builtins (PR #78729)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/78729 >From cc492d4134e4aa0aab56d01b21ec85937e49acfd Mon Sep 17 00:00:00 2001 From: Mariusz Sikora Date: Fri, 19 Jan 2024 16:29:46 +0100 Subject: [PATCH] [AMDGPU][GFX12] Add tests for unsupported builtins

[clang] [AMDGPU][GFX12] Add tests for unsupported builtins (PR #78729)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/78729 >From 19e0554bcebf739f7ad500f64efe62b38781f7a1 Mon Sep 17 00:00:00 2001 From: Mariusz Sikora Date: Fri, 19 Jan 2024 16:29:46 +0100 Subject: [PATCH] [AMDGPU][GFX12] Add tests for unsupported builtins

[clang] [AMDGPU][GFX12] Add tests for unsupported builtins (PR #78729)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/78729 >From 56cf06f1b530d5ec62de1cc3818bf2f76dfd Mon Sep 17 00:00:00 2001 From: Mariusz Sikora Date: Fri, 19 Jan 2024 16:29:46 +0100 Subject: [PATCH] [AMDGPU][GFX12] Add tests for unsupported builtins

[clang] [libc] [compiler-rt] [libcxx] [lldb] [pstl] [flang] [clang-tools-extra] [mlir] [openmp] [lld] [llvm] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

Mirko =?utf-8?q?Brkušanin?= , Mirko =?utf-8?q?Brkušanin?= ,Mirko Brkusanin ,Mariusz Sikora Message-ID: In-Reply-To: https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/78414 ___ cfe-commits mailing list cfe-comm

[clang] [AMDGPU][GFX12] Add tests for unsupported builtins (PR #78729)

@@ -4,10 +4,114 @@ typedef unsigned int uint; -kernel void test_builtins_amdgcn_gws_insts(uint a, uint b) { +#pragma OPENCL EXTENSION cl_khr_fp64:enable + +typedef float v2f __attribute__((ext_vector_type(2))); +typedef float v4f __attribute__((ext_vector_type(4))); +ty

[clang] [AMDGPU][GFX12] Add tests for unsupported builtins (PR #78729)

mariusz-sikora-at-amd wrote: ping https://github.com/llvm/llvm-project/pull/78729 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[lldb] [flang] [clang-tools-extra] [libcxx] [clang] [lld] [llvm] [compiler-rt] [libc] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

Mirko =?utf-8?q?Brkušanin?= , Mirko =?utf-8?q?Brkušanin?= ,Mirko Brkusanin ,Mariusz Sikora Message-ID: In-Reply-To: @@ -8770,6 +8781,22 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, } } +int VdstInIdx = AMDGPU::getNamedOper

[flang] [lld] [clang-tools-extra] [compiler-rt] [llvm] [libcxx] [lldb] [libc] [clang] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

mariusz-sikora-at-amd wrote: > > Correct, some of these instructions use opsel[1] which in LLVM in stored in > > src1_modifiers so a dummy src1 is used. > > Why can't we just use `SRCMODS.OP_SEL_1` with src0? When referring to `SRCMODS.OP_SEL_1` you are referring to `src1_modifier` (second bi

[clang] [lldb] [flang] [lld] [libc] [libcxx] [compiler-rt] [llvm] [clang-tools-extra] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

https://github.com/mariusz-sikora-at-amd edited https://github.com/llvm/llvm-project/pull/78414 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [lldb] [flang] [lld] [libc] [libcxx] [compiler-rt] [llvm] [clang-tools-extra] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

@@ -626,11 +629,82 @@ class Cvt_PK_F32_F8_Pat; -foreach Index = [0, -1] in { - def : Cvt_PK_F32_F8_Pat; - def : Cvt_PK_F32_F8_Pat; +let SubtargetPredicate = isGFX9Only in { + foreach Index = [0, -1] in { +def : Cvt_PK_F32_F8_Pat; +def : Cvt_PK_F32_F8_Pat; + } +} + +

[clang] [AMDGPU][GFX12] Add tests for unsupported builtins (PR #78729)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/78729 >From eb04956ce8ad84206a95789885003dd6c6f60d2e Mon Sep 17 00:00:00 2001 From: Mariusz Sikora Date: Fri, 19 Jan 2024 16:29:46 +0100 Subject: [PATCH] [AMDGPU][GFX12] Add tests for unsupported builtins

[libc] [flang] [compiler-rt] [llvm] [clang-tools-extra] [lldb] [clang] [libcxx] [lld] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

mariusz-sikora-at-amd wrote: > Why is so there so much special casing in the assembler/disassembler? I'm not an original author of these change, but from what I understand it is a workaround to handle VOP3 instructions which have a single source but require the use of two bits from OPSEL. `V_C

[clang-tools-extra] [compiler-rt] [lldb] [clang] [libcxx] [llvm] [flang] [lld] [libc] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

mariusz-sikora-at-amd wrote: > Can you add a GFX12 RUN line to > clang/test/CodeGenOpenCL/builtins-amdgcn-fp8.cl? That will probably require > adding "fp8-conversion-insts" to the GFX12 part of TargetParser.cpp. You can > do this in a separate patch if you want. Done https://github.com/llvm/

[clang] [AMDGPU][GFX12] Add tests for unsupported builtins (PR #78729)

https://github.com/mariusz-sikora-at-amd created https://github.com/llvm/llvm-project/pull/78729 __builtin_amdgcn_mfma* and __builtin_amdgcn_smfmac* >From d5a823584487d9f6b3e9bebc8976c7891243f470 Mon Sep 17 00:00:00 2001 From: Mariusz Sikora Date: Fri, 19 Jan 2024 16:29:46 +0100 Subject: [PATC

[clang] [libc] [libcxx] [clang-tools-extra] [flang] [compiler-rt] [llvm] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/75917 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [libc] [lld] [compiler-rt] [libcxx] [clang-tools-extra] [flang] [lldb] [llvm] AMDGPU/GFX12: Add new dot4 fp8/bf8 instructions (PR #77892)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/77892 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[libcxx] [llvm] [clang-tools-extra] [libc] [clang] [flang] [compiler-rt] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

@@ -1,56 +1,244 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s -; RUN: llc -march=amdgcn -global-isel=1 -mcpu=gfx1200 -verify-machineinstrs <

[lldb] [clang] [compiler-rt] [flang] [lld] [llvm] [libcxx] [libc] [clang-tools-extra] AMDGPU/GFX12: Add new dot4 fp8/bf8 instructions (PR #77892)

mariusz-sikora-at-amd wrote: Rebase to run tests https://github.com/llvm/llvm-project/pull/77892 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[lldb] [clang] [compiler-rt] [flang] [lld] [llvm] [libcxx] [libc] [clang-tools-extra] AMDGPU/GFX12: Add new dot4 fp8/bf8 instructions (PR #77892)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/77892 >From 628a3d2b42cdcbd903e0830ab7d631ea7dc422b9 Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Wed, 10 Jan 2024 12:17:58 +0100 Subject: [PATCH 1/2] AMDGPU/GFX12: Add new dot4 fp8/bf8 instructio

[clang] [llvm] [AMDGPU][NFC] Rename feature FP8Insts to FP8ConversionInsts (PR #78439)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/78439 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang-tools-extra] [clang] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/76224 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU][NFC] Rename feature FP8Insts to FP8ConversionInsts (PR #78439)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/78439 >From 5bd1644ec60996fed50c843e13e68f7c2c6dda81 Mon Sep 17 00:00:00 2001 From: Mariusz Sikora Date: Wed, 17 Jan 2024 13:19:55 +0100 Subject: [PATCH 1/2] [AMDGPU][NFC] Rename feature FP8Insts to FP8C

[llvm] [clang] [AMDGPU][NFC] Rename feature FP8Insts to FP8ConversionInsts (PR #78439)

https://github.com/mariusz-sikora-at-amd created https://github.com/llvm/llvm-project/pull/78439 None >From 5bd1644ec60996fed50c843e13e68f7c2c6dda81 Mon Sep 17 00:00:00 2001 From: Mariusz Sikora Date: Wed, 17 Jan 2024 13:19:55 +0100 Subject: [PATCH] [AMDGPU][NFC] Rename feature FP8Insts to FP8

[clang-tools-extra] [llvm] [clang] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/76224 >From 89b94cc98e188142cff11d58f27fe6c25183b376 Mon Sep 17 00:00:00 2001 From: Vang Thao Date: Thu, 21 Dec 2023 11:58:47 +0100 Subject: [PATCH 1/6] [AMDGPU][GFX12] Add Atomic cond_sub_u32 --- llvm/

[clang-tools-extra] [llvm] [clang] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

@@ -1182,6 +1182,11 @@ The AMDGPU backend implements the following LLVM IR intrinsics. The iglp_opt strategy implementations are subject to change. + llvm.atomic.cond.sub.u32 Provides direct access

[clang-tools-extra] [clang] [llvm] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/76224 >From 89b94cc98e188142cff11d58f27fe6c25183b376 Mon Sep 17 00:00:00 2001 From: Vang Thao Date: Thu, 21 Dec 2023 11:58:47 +0100 Subject: [PATCH 1/5] [AMDGPU][GFX12] Add Atomic cond_sub_u32 --- llvm/

[clang] [clang-tools-extra] [llvm] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

@@ -2502,10 +2500,9 @@ def int_amdgcn_flat_atomic_fmax_num : AMDGPUAtomicRtn; def int_amdgcn_global_atomic_fmin_num : AMDGPUAtomicRtn; def int_amdgcn_global_atomic_fmax_num : AMDGPUAtomicRtn; -def int_amdgcn_flat_atomic_cond_sub_u32 : AMDGPUAtomicRtn; -def int_amdgcn_global

[clang] [clang-tools-extra] [llvm] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/76224 >From 89b94cc98e188142cff11d58f27fe6c25183b376 Mon Sep 17 00:00:00 2001 From: Vang Thao Date: Thu, 21 Dec 2023 11:58:47 +0100 Subject: [PATCH 1/4] [AMDGPU][GFX12] Add Atomic cond_sub_u32 --- llvm/

[clang-tools-extra] [llvm] [clang] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

@@ -1368,6 +1391,28 @@ def int_amdgcn_struct_ptr_buffer_atomic_cmpswap : Intrinsic< // gfx908 intrinsic def int_amdgcn_struct_buffer_atomic_fadd : AMDGPUStructBufferAtomic; def int_amdgcn_struct_ptr_buffer_atomic_fadd : AMDGPUStructPtrBufferAtomic; +// gfx12 intrinsic +def i

[clang-tools-extra] [llvm] [clang] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

@@ -27,34 +27,23 @@ main_body: ret float %out0 } -define amdgpu_ps float @atomic_pk_add_bf16_1d_v2(<8 x i32> inreg %rsrc, <2 x i16> %data, i32 %s) { +define amdgpu_ps float @atomic_pk_add_bf16_1d_v2(<8 x i32> inreg %rsrc, <2 x bfloat> %data, i32 %s) { ; GFX12-LABEL: atomi

[clang] [llvm] AMDGPU/GFX12: Add new dot4 fp8/bf8 instructions (PR #77892)

@@ -2696,6 +2696,25 @@ def int_amdgcn_udot8 : ImmArg>, ImmArg>, ImmArg>] >; +// f32 %r = llvm.amdgcn.dot4.f32.type_a.type_b (v4type_a (as i32) %a, v4type_b (as i32) %b, f32 %c) +// %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + %c +class AMDGPU

[clang] [llvm] AMDGPU/GFX12: Add new dot4 fp8/bf8 instructions (PR #77892)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/77892 >From 628a3d2b42cdcbd903e0830ab7d631ea7dc422b9 Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Wed, 10 Jan 2024 12:17:58 +0100 Subject: [PATCH 1/2] AMDGPU/GFX12: Add new dot4 fp8/bf8 instructio

[llvm] [clang] [clang-tools-extra] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

mariusz-sikora-at-amd wrote: > Missing UniformityAnalysis test for these Done https://github.com/llvm/llvm-project/pull/76224 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [clang-tools-extra] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/76224 >From 89b94cc98e188142cff11d58f27fe6c25183b376 Mon Sep 17 00:00:00 2001 From: Vang Thao Date: Thu, 21 Dec 2023 11:58:47 +0100 Subject: [PATCH 1/3] [AMDGPU][GFX12] Add Atomic cond_sub_u32 --- llvm/

[llvm] [clang] [clang-tools-extra] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

mariusz-sikora-at-amd wrote: ping https://github.com/llvm/llvm-project/pull/76224 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [clang-tools-extra] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

mariusz-sikora-at-amd wrote: What is the plan for atomic_{flat/ds/global}_bf16 builtins ? Right now they are accepting <2 x i16> instead of <2 x bfloat>. Do we want to create new builtins or we want to override them to accept both <2 x i16> and <2 x bfloat> ? https://github.com/llvm/llvm-proj

[clang] [llvm] [clang-tools-extra] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

@@ -27,34 +27,23 @@ main_body: ret float %out0 } -define amdgpu_ps float @atomic_pk_add_bf16_1d_v2(<8 x i32> inreg %rsrc, <2 x i16> %data, i32 %s) { +define amdgpu_ps float @atomic_pk_add_bf16_1d_v2(<8 x i32> inreg %rsrc, <2 x bfloat> %data, i32 %s) { ; GFX12-LABEL: atomi

[clang] [llvm] [clang-tools-extra] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

@@ -362,24 +358,34 @@ define amdgpu_ps void @struct_buffer_atomic_add_v2f16_noret(<2 x half> %val, <4 ret void } -define amdgpu_ps float @struct_buffer_atomic_add_v2bf16_ret(<2 x i16> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { +define amd

[clang] [llvm] [clang-tools-extra] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

@@ -0,0 +1,92 @@ +// RUN: %clang_cc1 -O0 -cl-std=CL2.0 -triple amdgcn-amd-amdhsa -target-cpu gfx1200 \ +// RUN: %s -S -emit-llvm -o - | FileCheck %s + +// RUN: %clang_cc1 -O0 -cl-std=CL2.0 -triple amdgcn-amd-amdhsa -target-cpu gfx1200 \ +// RUN: -S -o - %s | FileCheck -check

[clang] [llvm] AMDGPU/GFX12: Add new dot4 fp8/bf8 instructions (PR #77892)

https://github.com/mariusz-sikora-at-amd created https://github.com/llvm/llvm-project/pull/77892 Endoding is VOP3P. Tagged as deep/machine learning instructions. i32 type (v4fp8 or v4bf8 packed in i32) is used for src0 and src1. src0 and src1 have no src_modifiers. src2 is f32 and has src_modi

[llvm] [clang-tools-extra] [clang] [AMDGPU][GFX12] Default component broadcast store (PR #76212)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/76212 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang-tools-extra] [llvm] [clang] [AMDGPU][GFX12] Default component broadcast store (PR #76212)

mariusz-sikora-at-amd wrote: Merge with upstream to run tests. I will merge this changes if CI will pass. https://github.com/llvm/llvm-project/pull/76212 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/lis

[clang-tools-extra] [clang] [llvm] [AMDGPU][GFX12] Default component broadcast store (PR #76212)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/76212 >From 06117c6124e94953f62eff3b1b87d98146f9e25e Mon Sep 17 00:00:00 2001 From: Mateja Marjanovic Date: Wed, 10 May 2023 16:24:38 +0200 Subject: [PATCH 1/2] [AMDGPU][GFX12] Default component broadcast

[clang-tools-extra] [llvm] [clang] [AMDGPU][GFX12] Default component broadcast store (PR #76212)

mariusz-sikora-at-amd wrote: ping @arsenm https://github.com/llvm/llvm-project/pull/76212 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [clang-tools-extra] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

mariusz-sikora-at-amd wrote: Adding support in atomicrmw. This will require to add new operation to aromicrmw "cond_sub" or you had something else in mind @arsenm ? https://github.com/llvm/llvm-project/pull/76224 ___ cfe-commits mailing list cfe-commi

[clang] [llvm] [clang-tools-extra] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

@@ -2502,10 +2500,9 @@ def int_amdgcn_flat_atomic_fmax_num : AMDGPUAtomicRtn; def int_amdgcn_global_atomic_fmin_num : AMDGPUAtomicRtn; def int_amdgcn_global_atomic_fmax_num : AMDGPUAtomicRtn; -def int_amdgcn_flat_atomic_cond_sub_u32 : AMDGPUAtomicRtn; -def int_amdgcn_global

[clang] [llvm] [clang-tools-extra] [AMDGPU][GFX12] Add Atomic cond_sub_u32 (PR #76224)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/76224 >From 89b94cc98e188142cff11d58f27fe6c25183b376 Mon Sep 17 00:00:00 2001 From: Vang Thao Date: Thu, 21 Dec 2023 11:58:47 +0100 Subject: [PATCH 1/2] [AMDGPU][GFX12] Add Atomic cond_sub_u32 --- llvm/

[llvm] [clang] [clang-tools-extra] [AMDGPU][GFX12] Default component broadcast store (PR #76212)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/76212 >From 06117c6124e94953f62eff3b1b87d98146f9e25e Mon Sep 17 00:00:00 2001 From: Mateja Marjanovic Date: Wed, 10 May 2023 16:24:38 +0200 Subject: [PATCH 1/2] [AMDGPU][GFX12] Default component broadcast

[clang-tools-extra] [llvm] [AMDGPU] Quit PromoteAllocaToVector if intrinsic is used (PR #68744)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/68744 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

@@ -0,0 +1,92 @@ +// RUN: %clang_cc1 -O0 -cl-std=CL2.0 -triple amdgcn-amd-amdhsa -target-cpu gfx1200 \ +// RUN: %s -S -emit-llvm -o - | FileCheck %s + +// RUN: %clang_cc1 -O0 -cl-std=CL2.0 -triple amdgcn-amd-amdhsa -target-cpu gfx1200 \ mariusz-sikora-at-amd w

[clang-tools-extra] [llvm] [AMDGPU] Quit PromoteAllocaToVector if intrinsic is used (PR #68744)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/68744 >From 3dc3a43193247015933392b7da76c4ef77268231 Mon Sep 17 00:00:00 2001 From: Mariusz Sikora Date: Tue, 10 Oct 2023 21:50:48 +0200 Subject: [PATCH 1/2] [AMDGPU] Bail if assume-like intrinsic is used

[clang] [llvm] [AMDGPU][GFX12] Add 16 bit atomic fadd instructions (PR #75917)

https://github.com/mariusz-sikora-at-amd created https://github.com/llvm/llvm-project/pull/75917 - image_atomic_pk_add_f16 - image_atomic_pk_add_bf16 - ds_pk_add_bf16 - ds_pk_add_f16 - ds_pk_add_rtn_bf16 - ds_pk_add_rtn_f16 - flat_atomic_pk_add_f16 - flat_atomic_pk_add_bf16 - global_atomic_pk_ad

[lldb] [clang] [compiler-rt] [libcxx] [flang] [lld] [clang-tools-extra] [mlir] [llvm] [libc] GFX12: Add LoopDataPrefetchPass (PR #75625)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/75625 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [lldb] [libc] [clang] [flang] [clang-tools-extra] [libcxx] [mlir] [compiler-rt] [lld] GFX12: Add LoopDataPrefetchPass (PR #75625)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/75625 >From de5303eb8a9e061dbd365922f85cad02bca5ec26 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Tue, 5 Jul 2022 11:41:29 -0700 Subject: [PATCH 1/4] GFX12: Add LoopDataPrefetchPass It is c

[llvm] [lldb] [libc] [clang] [flang] [clang-tools-extra] [libcxx] [mlir] [compiler-rt] [lld] GFX12: Add LoopDataPrefetchPass (PR #75625)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/75625 >From de5303eb8a9e061dbd365922f85cad02bca5ec26 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Tue, 5 Jul 2022 11:41:29 -0700 Subject: [PATCH 1/3] GFX12: Add LoopDataPrefetchPass It is c

[llvm] [lld] [clang] [compiler-rt] [libcxxabi] [lldb] [clang-tools-extra] [flang] [libcxx] [AMDGPU] GFX12: select @llvm.prefetch intrinsic (PR #74576)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/74576 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[flang] [clang] [lldb] [libcxxabi] [lld] [compiler-rt] [clang-tools-extra] [llvm] [libcxx] [AMDGPU] GFX12: select @llvm.prefetch intrinsic (PR #74576)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/74576 >From 23759746b66c33028ad2340b1e98067ebf1f8074 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Tue, 28 Jun 2022 15:24:24 -0700 Subject: [PATCH 1/4] [AMDGPU] GFX12: select @llvm.prefetch i

[clang] [llvm] [clang-tools-extra] [libc] [compiler-rt] [libcxx] [lldb] [mlir] [flang] [lld] [AMDGPU] GFX12: Add Split Workgroup Barrier (PR #74836)

@@ -684,6 +684,51 @@ s_rndne_f16 s5, 0xfe0b s_rndne_f16 s5, 0x3456 // GFX12: encoding: [0xff,0x6e,0x85,0xbe,0x56,0x34,0x00,0x00] +s_barrier_signal -2 mariusz-sikora-at-amd wrote: Patch: https://github.com/llvm/llvm-project/pull/75575 https://github.com/llvm/

[clang] [llvm] [AMDGPU][GFX12] Add new v_permlane16 variants (PR #75475)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/75475 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU][GFX12] Add new v_permlane16 variants (PR #75475)

mariusz-sikora-at-amd wrote: > LGTM > > You could also update existing permlane tests with run lines for gfx12: > > * test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll > > * test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir > > > This can also be a separate patch. New patch: https://github.co

[llvm] [libcxx] [clang] [clang-tools-extra] [lldb] [libc] [flang] [mlir] [compiler-rt] [lld] [AMDGPU] GFX12: Add Split Workgroup Barrier (PR #74836)

@@ -684,6 +684,51 @@ s_rndne_f16 s5, 0xfe0b s_rndne_f16 s5, 0x3456 // GFX12: encoding: [0xff,0x6e,0x85,0xbe,0x56,0x34,0x00,0x00] +s_barrier_signal -2 mariusz-sikora-at-amd wrote: Thanks ! https://github.com/llvm/llvm-project/pull/74836 __

[clang] [llvm] [AMDGPU][GFX12] Add new v_permlane16 variants (PR #75475)

https://github.com/mariusz-sikora-at-amd created https://github.com/llvm/llvm-project/pull/75475 None >From c878aa8f2e331cf8c88ab6e191db663ed56d9ce7 Mon Sep 17 00:00:00 2001 From: Mariusz Sikora Date: Thu, 14 Dec 2023 11:13:36 +0100 Subject: [PATCH] [AMDGPU][GFX12] Add new v_permlane16 variant

[clang-tools-extra] [mlir] [flang] [lld] [libc] [llvm] [compiler-rt] [libcxx] [lldb] [clang] [AMDGPU] GFX12: Add Split Workgroup Barrier (PR #74836)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/74836 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[compiler-rt] [clang-tools-extra] [libcxx] [llvm] [flang] [clang] [libc] [AMDGPU] Update VOP instructions for GFX12 (PR #74853)

https://github.com/mariusz-sikora-at-amd closed https://github.com/llvm/llvm-project/pull/74853 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AMDGPU] GFX12: Add Split Workgroup Barrier (PR #74836)

mariusz-sikora-at-amd wrote: ping https://github.com/llvm/llvm-project/pull/74836 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[libcxx] [flang] [clang-tools-extra] [libcxxabi] [compiler-rt] [clang] [lldb] [lld] [llvm] [AMDGPU] GFX12: select @llvm.prefetch intrinsic (PR #74576)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/74576 >From 23759746b66c33028ad2340b1e98067ebf1f8074 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Tue, 28 Jun 2022 15:24:24 -0700 Subject: [PATCH 1/2] [AMDGPU] GFX12: select @llvm.prefetch i

[libcxxabi] [flang] [lld] [llvm] [compiler-rt] [lldb] [clang] [clang-tools-extra] [libcxx] [AMDGPU] GFX12: select @llvm.prefetch intrinsic (PR #74576)

@@ -959,6 +967,32 @@ def : GCNPat < } } // let OtherPredicates = [HasShaderCyclesRegister] +def SIMM24bitPtr : ImmLeaf (Imm);}] +>; + +multiclass SMPrefetchPat { + def : GCNPat < +(smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32 cache_type)), +(!cas

[libcxxabi] [flang] [clang-tools-extra] [libcxx] [lldb] [clang] [llvm] [compiler-rt] [lld] [AMDGPU] GFX12: select @llvm.prefetch intrinsic (PR #74576)

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/74576 >From 23759746b66c33028ad2340b1e98067ebf1f8074 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Tue, 28 Jun 2022 15:24:24 -0700 Subject: [PATCH] [AMDGPU] GFX12: select @llvm.prefetch intri

[clang] 69061f9 - [AMDGPU] Add clang builtin for __builtin_amdgcn_ds_atomic_fadd_v2f16

Author: Mariusz Sikora Date: 2023-03-24T16:27:44+01:00 New Revision: 69061f96275c3053623a8699ce641c0f0ac61aed URL: https://github.com/llvm/llvm-project/commit/69061f96275c3053623a8699ce641c0f0ac61aed DIFF: https://github.com/llvm/llvm-project/commit/69061f96275c3053623a8699ce641c0f0ac61aed.diff

[clang] ea064ee - [AMDGPU] Create Subtarget Features for some of 16 bits atomic fadd instructions

Author: Mariusz Sikora Date: 2023-03-24T13:10:40+01:00 New Revision: ea064ee2a3bd22f5598d0eb76a1bbc3bf293b063 URL: https://github.com/llvm/llvm-project/commit/ea064ee2a3bd22f5598d0eb76a1bbc3bf293b063 DIFF: https://github.com/llvm/llvm-project/commit/ea064ee2a3bd22f5598d0eb76a1bbc3bf293b063.diff