https://github.com/mbrkusanin closed
https://github.com/llvm/llvm-project/pull/77795
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mbrkusanin wrote:
Rebased and updated after https://github.com/llvm/llvm-project/pull/76143
https://github.com/llvm/llvm-project/pull/77795
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mbrkusanin wrote:
Rebased and reverted bfloat
https://github.com/llvm/llvm-project/pull/77795
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@@ -2601,67 +2601,73 @@ def int_amdgcn_ds_bvh_stack_rtn :
[ImmArg>, IntrWillReturn, IntrNoCallback, IntrNoFree]
>;
+def int_amdgcn_s_wait_event_export_ready :
+ ClangBuiltin<"__builtin_amdgcn_s_wait_event_export_ready">,
+ Intrinsic<[], [], [IntrNoMem,
mbrkusanin wrote:
Ping
https://github.com/llvm/llvm-project/pull/77795
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@@ -305,6 +305,11 @@ class VOP3OpSel_gfx10 op, VOPProfile p> :
VOP3e_gfx10 {
class VOP3OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3OpSel_gfx10;
+class VOP3FP8OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3e_gfx10
{
+ let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0);
+ let
@@ -305,6 +305,11 @@ class VOP3OpSel_gfx10 op, VOPProfile p> :
VOP3e_gfx10 {
class VOP3OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3OpSel_gfx10;
+class VOP3FP8OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3e_gfx10
{
+ let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0);
+ let
@@ -253,22 +253,22 @@ def ROCDL_mfma_f32_32x32x16_fp8_fp8 :
ROCDL_Mfma_IntrOp<"mfma.f32.32x32x16.fp8.f
//===-===//
// WMMA intrinsics
-class ROCDL_Wmma_IntrOp traits = []> :
+class ROCDL_Wmma_IntrOp
mbrkusanin wrote:
If there are no further comments, should I merge this?
https://github.com/llvm/llvm-project/pull/77795
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@@ -305,6 +305,11 @@ class VOP3OpSel_gfx10 op, VOPProfile p> :
VOP3e_gfx10 {
class VOP3OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3OpSel_gfx10;
+class VOP3FP8OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3e_gfx10
{
+ let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0);
+ let
@@ -253,22 +253,22 @@ def ROCDL_mfma_f32_32x32x16_fp8_fp8 :
ROCDL_Mfma_IntrOp<"mfma.f32.32x32x16.fp8.f
//===-===//
// WMMA intrinsics
-class ROCDL_Wmma_IntrOp traits = []> :
+class ROCDL_Wmma_IntrOp
mbrkusanin wrote:
> > Correct, some of these instructions use opsel[1] which in LLVM in stored in
> > src1_modifiers so a dummy src1 is used.
>
> Why can't we just use `SRCMODS.OP_SEL_1` with src0?
That could work. We would have to make custom encoding classes then since
OP_SEL_1 would have
@@ -626,11 +629,82 @@ class Cvt_PK_F32_F8_Pat;
-foreach Index = [0, -1] in {
- def : Cvt_PK_F32_F8_Pat;
- def : Cvt_PK_F32_F8_Pat;
+let SubtargetPredicate = isGFX9Only in {
+ foreach Index = [0, -1] in {
+def : Cvt_PK_F32_F8_Pat;
+def : Cvt_PK_F32_F8_Pat;
+ }
+}
+
+
mbrkusanin wrote:
> > > Why is so there so much special casing in the assembler/disassembler?
> >
> >
> > I'm not an original author of these change, but from what I understand it
> > is a workaround to handle VOP3 instructions which have a single source but
> > require the use of two bits
mbrkusanin wrote:
> > Why is so there so much special casing in the assembler/disassembler?
>
> I'm not an original author of these change, but from what I understand it is
> a workaround to handle VOP3 instructions which have a single source but
> require the use of two bits from OPSEL.
mbrkusanin wrote:
Rebased.
https://github.com/llvm/llvm-project/pull/77795
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https://github.com/mbrkusanin approved this pull request.
https://github.com/llvm/llvm-project/pull/78709
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https://github.com/mbrkusanin approved this pull request.
https://github.com/llvm/llvm-project/pull/78155
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@@ -423,6 +423,67 @@ TARGET_BUILTIN(__builtin_amdgcn_s_wakeup_barrier, "vi",
"n", "gfx12-insts")
TARGET_BUILTIN(__builtin_amdgcn_s_barrier_leave, "b", "n", "gfx12-insts")
TARGET_BUILTIN(__builtin_amdgcn_s_get_barrier_state, "Uii", "n", "gfx12-insts")
mbrkusanin wrote:
Note that the first commit in this PR is:
https://github.com/llvm/llvm-project/pull/77785
https://github.com/llvm/llvm-project/pull/77795
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