[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

mhorne added a comment. Herald added a subscriber: arichardson. Thanks Sam and Luis for the review. Could I ask that one of you commit this if you are able? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68362/new/ https://reviews.llvm.org/D68362

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

mhorne updated this revision to Diff 232721. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68362/new/ https://reviews.llvm.org/D68362 Files: libunwind/include/__libunwind_config.h libunwind/include/libunwind.h libunwind/src/Registers.hpp libunwind/src/UnwindCursor.hpp

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

mhorne added reviewers: compnerd, phosek. mhorne marked 2 inline comments as done. mhorne added a comment. Add some libunwind contributors for additional review. Comment at: libunwind/src/Registers.hpp:3756 +inline double Registers_riscv::getFloatRegister(int regNum) const {

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

mhorne marked 3 inline comments as done. mhorne added inline comments. Comment at: libunwind/include/__libunwind_config.h:26 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31 +#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 63 luismarques wrote: >

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

mhorne updated this revision to Diff 228799. mhorne marked an inline comment as done. mhorne added a comment. Convert checks for `__riscv_float_abi_double` to `__riscv_flen == 64`. Fix `_LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV`. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68362/new/

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

mhorne marked 2 inline comments as done. mhorne added inline comments. Comment at: libunwind/src/Registers.hpp:3756 +inline double Registers_riscv::getFloatRegister(int regNum) const { +#ifdef __riscv_float_abi_double + assert(validFloatRegister(regNum));

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

mhorne marked 5 inline comments as done. mhorne added a comment. Thanks for the review! Comment at: libunwind/src/Registers.hpp:3585 + +inline uint64_t Registers_riscv::getRegister(int regNum) const { + if (regNum == UNW_REG_IP) lenary wrote: > Do you want to

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

mhorne updated this revision to Diff 223971. mhorne added a comment. Address lenary's comments. Add a check for __riscv_float_abi_double in getFloat/setFloat. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68362/new/ https://reviews.llvm.org/D68362 Files:

[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

mhorne created this revision. Herald added subscribers: s.egerton, lenary, benna, psnobl, PkmX, rkruppe, rogfer01, shiva0217, christof, kito-cheng, simoncook, krytarowski, aprantl. Add unwinding support for 64-bit RISC-V. This is from the FreeBSD implementation with the following minor changes:

[PATCH] D61098: [clang] [RISC-V] Add validation for inline assembly constraints

mhorne abandoned this revision. mhorne added a comment. Herald added subscribers: pzheng, s.egerton, lenary, MaskRay. This has been handled more correctly and completely with recent patches. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D61098/new/

[PATCH] D61098: [clang] [RISC-V] Add validation for inline assembly constraints

mhorne added a comment. Apologies if I didn't tag the right reviewers; I took a look at those who seemed to be most involved with the RISC-V target, but if there's anyone more appropriate to review clang changes then feel free to add them instead :) Repository: rG LLVM Github Monorepo

[PATCH] D61098: [clang] [RISC-V] Add validation for inline assembly constraints

mhorne created this revision. mhorne added reviewers: asb, apazos, shiva0217. Herald added subscribers: cfe-commits, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar. Herald added a project: