[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: > > Should we use strings like ARM does so we can get register by name? > > Good point! We may provide two kinds of builtins: one by name, and another by > CSR number. We should continue @lenary's proposal and discuss it in >

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: > You can just use `({ ... })` to achieve that same goal with inline assembly > (and write doesn't even need that, you can do it with a single statement). > I'm not convinced the intrinsics gain you anything. Hmm... I think there's a bit of a disconnect here between the point

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: > > > I have always been unconvinced that these are a good idea to have / add > > > significant value over using inline assembly. IIRC Arm has them but > > > nobody uses them? ... > If it’s not a constant integer for inline assembly then how would it > magically be a

[clang] [DRAFT][RISCV] Emit arch string macro to facilitate ASM programming (PR #85063)

nemanjai wrote: Ah, I missed the fact that there is an option `-riscv-add-build-attributes` that the clang driver passes when invoking `cc1as`. Perhaps that option should default to `true`? Thanks and sorry for the noise. https://github.com/llvm/llvm-project/pull/85063

[clang] [DRAFT][RISCV] Emit arch string macro to facilitate ASM programming (PR #85063)

https://github.com/nemanjai closed https://github.com/llvm/llvm-project/pull/85063 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

@@ -74,6 +74,21 @@ let TargetPrefix = "riscv" in { } // TargetPrefix = "riscv" +let TargetPrefix = "riscv" in { + // Zicsr + def int_riscv_csrr : +DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem, IntrHasSideEffects, ImmArg>]>;

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

@@ -20,6 +20,12 @@ class RISCVBuiltin : TargetBuiltin { let Attributes = [NoThrow, Const] in { //===--===// +// Zicsr extension.

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: > I have always been unconvinced that these are a good idea to have / add > significant value over using inline assembly. IIRC Arm has them but nobody > uses them? Is this a comment about the general concept of builtins to produce specific instructions or about these specific

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: > > Individual implementations will provide different sets of CSR's and need a > > way to read/write them. Of course, this can be done with inline asm, but > > doing such things with inline asm has its limitations (no error checking, > > Wouldn't the assembler error check the

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: Individual implementations will provide different sets of CSR's and need a way to read/write them. Of course, this can be done with inline asm, but doing such things with inline asm has its limitations (no error checking, if a user attempts to wrap the asm in a function, they

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

https://github.com/nemanjai created https://github.com/llvm/llvm-project/pull/85091 To facilitate proper range checking and better error messages if an attempt is made to call these with non-litaral arguments, we provide builtins to emit the read/write CSR instructions. >From

[clang] [DRAFT][RISCV] Emit arch string macro to facilitate ASM programming (PR #85063)

nemanjai wrote: This is a suggestion born out of a request from a user to have a way to emit the ISA attributes into objects produced from pre-processed asm files. Perhaps there is already a method to do this that I'm not aware of, but if not, I think this is a convenient and lightweight way

[clang] [DRAFT][RISCV] Emit arch string macro to facilitate ASM programming (PR #85063)

https://github.com/nemanjai edited https://github.com/llvm/llvm-project/pull/85063 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Emit arch string macro to facilitate ASM programming (PR #85063)

https://github.com/nemanjai created https://github.com/llvm/llvm-project/pull/85063 In order to make assembly programming more convenient, emit macro __riscv_cmdline_arch_string that will be defined to the arch string based on the command line arguments. This string may differ from the actual

[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)

@@ -364,7 +364,14 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { // have Glibc since it is Glibc that provides the HWCAP[2] in the auxv. static constexpr int MINIMUM_AIX_OS_MAJOR = 7; static constexpr int MINIMUM_AIX_OS_MINOR = 2; - bool

[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)

@@ -141,23 +149,30 @@ PPC_LNX_CPU("power10",47) #define AIX_BUILTIN_PPC_TRUE 1 #define AIX_BUILTIN_PPC_FALSE 0 #define USE_SYS_CONF 2 + #define SYS_CALL 3 // Supported COMPARE_OP values. #define COMP_EQ 0 + #define COMP_GT 1 + #define COMP_GE 2 + #define

[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)

@@ -0,0 +1,171 @@ +// RUN: echo "int main() { return __builtin_cpu_supports(\"4xxmac\");}" > %t.c nemanjai wrote: This is an interesting way of testing, where we create each test on the fly. I am not against it if it works on all platforms (including Windows).

[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)

@@ -16570,32 +16570,72 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, #include "llvm/TargetParser/PPCTargetParser.def" auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx, nemanjai wrote: This is now a very

[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)

@@ -141,23 +149,30 @@ PPC_LNX_CPU("power10",47) #define AIX_BUILTIN_PPC_TRUE 1 #define AIX_BUILTIN_PPC_FALSE 0 #define USE_SYS_CONF 2 + #define SYS_CALL 3 // Supported COMPARE_OP values. #define COMP_EQ 0 + #define COMP_GT 1 + #define COMP_GE 2 + #define

[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)

nemanjai wrote: My review is not complete, I just submitted what I have so far so at least we can get started on answering the questions I have so far. https://github.com/llvm/llvm-project/pull/77732 ___ cfe-commits mailing list

[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)

@@ -486,7 +486,8 @@ std::unique_ptr createAIXTargetCodeGenInfo(CodeGenModule , bool Is64Bit); std::unique_ptr -createPPC32TargetCodeGenInfo(CodeGenModule , bool SoftFloatABI); +createPPC32TargetCodeGenInfo(CodeGenModule , bool SoftFloatABI, +

[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)

@@ -78,6 +78,13 @@ class CodeGenOptions : public CodeGenOptionsBase { SRCK_InRegs// Small structs in registers (-freg-struct-return). }; + enum ComplexArgumentConventionKind { +CMPLX_Default, +CMPLX_OnStack, +CMPLX_OnGPR, // if ppc32

[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)

@@ -2540,6 +2540,10 @@ def ffp_contract : Joined<["-"], "ffp-contract=">, Group, HelpText<"Form fused FP ops (e.g. FMAs)">, Values<"fast,on,off,fast-honor-pragmas">; +def fcomplex_ppc_gnu_abi : Flag<["-"], "fcomplex-ppc-gnu-abi">, Group, Visibility<[ClangOption,

[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, Intrinsic::ID ID = Intrinsic::not_intrinsic; +#include "llvm/TargetParser/PPCTargetParser.def" + auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op, +

[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, Intrinsic::ID ID = Intrinsic::not_intrinsic; +#include "llvm/TargetParser/PPCTargetParser.def" + auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op, +

[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

@@ -362,8 +362,18 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { // We support __builtin_cpu_supports/__builtin_cpu_is on targets that // have Glibc since it is Glibc that provides the HWCAP[2] in the auxv. +#define MINIMUM_AIX_OS_MAJOR 7

[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, Intrinsic::ID ID = Intrinsic::not_intrinsic; +#include "llvm/TargetParser/PPCTargetParser.def" nemanjai wrote: This is getting a bit tangled. Can you please provide

[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

@@ -10347,6 +10347,8 @@ def err_x86_builtin_tile_arg_duplicate : Error< def err_builtin_target_unsupported : Error< "builtin is not supported on this target">; +def err_builtin_aix_os_unsupported : Error< + "this builtin is available only in AIX 7.2 and later operating

[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

https://github.com/nemanjai edited https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

https://github.com/nemanjai commented: Do we really want to support only `__builtin_cpu_is` on AIX? It doesn't seem like this would achieve the desired goal. Most users will use these builtins to test for some capability on the target machine. It almost never really matters to a user whether

[clang] [Preprocessor] Fix __has_builtin for CPU ID functions (PR #80058)

https://github.com/nemanjai closed https://github.com/llvm/llvm-project/pull/80058 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

nemanjai wrote: Fix in https://github.com/llvm/llvm-project/pull/80058 https://github.com/llvm/llvm-project/pull/68919 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Preprocessor] Fix __has_builtin for CPU ID functions (PR #80058)

https://github.com/nemanjai created https://github.com/llvm/llvm-project/pull/80058 My recent commit (67c1c1d) made the CPU ID builtins target-independent so they can be used on PPC as well. However, that had the unintended consequence of changing the behaviour of __has_builtin in that it

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

nemanjai wrote: Sorry, I'll put up a patch for review shortly to fix this problem. https://github.com/llvm/llvm-project/pull/68919 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

https://github.com/nemanjai updated https://github.com/llvm/llvm-project/pull/68919 >From 65c84f2ba78efcbf92ce9c8232fc40f493414930 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Thu, 12 Oct 2023 14:08:42 -0400 Subject: [PATCH 1/5] [PowerPC][X86] Make cpu id builtins target independent

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -359,6 +359,13 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { bool isSPRegName(StringRef RegName) const override { return RegName.equals("r1") || RegName.equals("x1"); } + + // We support __builtin_cpu_supports/__builtin_cpu_is on targets

[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -16086,6 +16086,41 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, switch (BuiltinID) { default: return nullptr; + case Builtin::BI__builtin_cpu_is: { +const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts(); +StringRef CPUStr =

[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -210,6 +210,15 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". [llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_vararg_ty], [IntrNoMem]>; + // Load of a value provided by the system library

[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

https://github.com/nemanjai updated https://github.com/llvm/llvm-project/pull/68919 >From 71f1352bf00d6a9eefa3f199859d47d093f272f8 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Thu, 12 Oct 2023 14:08:42 -0400 Subject: [PATCH 1/4] [PowerPC][X86] Make cpu id builtins target independent

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema , SourceLocation Loc, return false; } +/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *). +/// This checks that the target supports __builtin_cpu_supports and +/// that the string

[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema , SourceLocation Loc, return false; } +/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *). +/// This checks that the target supports __builtin_cpu_supports and +/// that the string

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -15,38 +20,57 @@ int main(void) { if (__builtin_cpu_supports("sse4.2")) a("sse4.2"); - // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0) - // CHECK: [[AND:%[^ ]+]] = and i32

[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -3124,6 +3125,36 @@ bool PPCInstrInfo::expandPostRAPseudo(MachineInstr ) const { .addReg(Reg); return true; } + case PPC::PPCLdFixedAddr: { +assert(Subtarget.isTargetLinux() && + "Only Linux target is expected to contain PPCLdFixedAddr"); +

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -15,38 +20,57 @@ int main(void) { if (__builtin_cpu_supports("sse4.2")) a("sse4.2"); - // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0) - // CHECK: [[AND:%[^ ]+]] = and i32

[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -873,3 +873,17 @@ ArrayRef PPCTargetInfo::getTargetBuiltins() const { return llvm::ArrayRef(BuiltinInfo, clang::PPC::LastTSBuiltin - Builtin::FirstTSBuiltin); } + +bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const {

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -359,6 +359,13 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { bool isSPRegName(StringRef RegName) const override { return RegName.equals("r1") || RegName.equals("x1"); } + + // We support __builtin_cpu_supports/__builtin_cpu_is on targets

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema , SourceLocation Loc, return false; } +/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *). +/// This checks that the target supports __builtin_cpu_supports and +/// that the string

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema , SourceLocation Loc, return false; } +/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *). +/// This checks that the target supports __builtin_cpu_supports and +/// that the string

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -32,6 +32,7 @@ class PPCTargetMachine final : public LLVMTargetMachine { std::unique_ptr TLOF; PPCABI TargetABI; Endian Endianness = Endian::NOT_DETECTED; + mutable bool HasGlibcHWCAPAccess = false; nemanjai wrote: Target machine is not modifiable

[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema , SourceLocation Loc, return false; } +/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *). +/// This checks that the target supports __builtin_cpu_supports and +/// that the string

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -210,6 +210,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". [llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_vararg_ty], [IntrNoMem]>; + // Load of a value provided by the system library

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -1,11 +1,16 @@ -// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s| FileCheck %s +// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s | FileCheck %s \ +// RUN: --check-prefix=CHECK-X86 +// RUN: %clang_cc1 -triple ppc64le-linux-gnu -emit-llvm < %s |

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -1830,6 +1830,10 @@ void PPCLinuxAsmPrinter::emitEndOfAsmFile(Module ) { PPCTargetStreamer *TS = static_cast(OutStreamer->getTargetStreamer()); + if (static_cast(TM).hasGlibcHWCAPAccess()) nemanjai wrote: Ha ha, more as in "any"?

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -0,0 +1,80 @@ +#ifndef PPC_FEATURE nemanjai wrote: Sounds good. https://github.com/llvm/llvm-project/pull/68919 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema , SourceLocation Loc, return false; } +/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *). +/// This checks that the target supports __builtin_cpu_supports and +/// that the string

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

https://github.com/nemanjai updated https://github.com/llvm/llvm-project/pull/68919 >From 71f1352bf00d6a9eefa3f199859d47d093f272f8 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Thu, 12 Oct 2023 14:08:42 -0400 Subject: [PATCH 1/3] [PowerPC][X86] Make cpu id builtins target independent

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

https://github.com/nemanjai approved this pull request. My comments have been addressed, so this LGTM. I'll of course defer to @asb and @topperc for final approval. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction , }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) nemanjai wrote: Sounds good. Maybe just a little comment

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -50,11 +50,14 @@ void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) { void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo , bool EmitStackAlign) { - if (STI.hasFeature(RISCV::FeatureRVE)) -

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -179,6 +180,11 @@ Assembly Support Supported Fully supported by the compiler. This includes everything in Assembly Support, along with - if relevant - C language intrinsics for the instructions and pattern matching by the compiler to recognize idiomatic patterns which

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -17,6 +17,13 @@ def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">, AssemblerPredicate<(all_of FeatureStdExtZicsr), "'Zicsr' (CSRs)">; +def FeatureStdExtI +: SubtargetFeature<"i", "HasStdExtI",

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction , }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) nemanjai wrote: What happens if we are using

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -83,13 +88,14 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { } BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction ) const { + const RISCVSubtarget = MF.getSubtarget(); nemanjai wrote: Why was this added? Or

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -38,3 +40,14 @@ def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, // Same as CSR_Interrupt, but including all 64-bit FP registers. def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, (sequence "F%u_D",

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

https://github.com/nemanjai edited https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

https://github.com/nemanjai commented: It is not my intent to hold up approval of this patch. In addition to the minor comments I added, I plan to do some local testing but even if the testing reveals issues, they can be fixed on subsequent commits.

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

nemanjai wrote: > @nemanjai I'm curious if you have an interest / need to support RVE or not? I most certainly do. Thank you for alerting me to this PR. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list

[clang] [PowerPC] Fix use of FPSCR builtins in smmintrin.h (PR #67299)

@@ -11595,6 +11595,50 @@ SDValue PPCTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG ) const { llvm_unreachable("ERROR:Should return for all cases within swtich."); } +// Lower mffsl intrinsic with mffs in targets without ISA 3.0 +static SDValue lowerMFFSL(SDValue

[clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

https://github.com/nemanjai updated https://github.com/llvm/llvm-project/pull/68919 >From 71f1352bf00d6a9eefa3f199859d47d093f272f8 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Thu, 12 Oct 2023 14:08:42 -0400 Subject: [PATCH 1/2] [PowerPC][X86] Make cpu id builtins target independent

[clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

https://github.com/nemanjai created https://github.com/llvm/llvm-project/pull/68919 Make __builtin_cpu_{init|supports|is} target independent and provide an opt-in query for targets that want to support it. Each target is still responsible for their specific lowering/code-gen. Also provide

[clang-tools-extra] ffd7a20 - [clang-tidy] Fix build bot break after 474a2b9367ad

Author: Nemanja Ivanovic Date: 2023-06-14T06:47:34-05:00 New Revision: ffd7a200fdfbd01ef296101647d2f2da91ddfd41 URL: https://github.com/llvm/llvm-project/commit/ffd7a200fdfbd01ef296101647d2f2da91ddfd41 DIFF:

[clang] 59cd692 - [PowerPC] Recognize long CPU name for -mtune in Clang

Author: Nemanja Ivanovic Date: 2023-03-02T14:29:40-05:00 New Revision: 59cd692454c9430f0fb77ca14b65cb9afcfe2776 URL: https://github.com/llvm/llvm-project/commit/59cd692454c9430f0fb77ca14b65cb9afcfe2776 DIFF:

[libunwind] 372820b - [libunwind][PowerPC] Fix saving/restoring VSX registers on LE systems

Author: Nemanja Ivanovic Date: 2023-02-16T13:37:58-05:00 New Revision: 372820bf571c8d32c8165cfc74b0439c7bb397f9 URL: https://github.com/llvm/llvm-project/commit/372820bf571c8d32c8165cfc74b0439c7bb397f9 DIFF:

[clang] 1013967 - [PowerPC] Remove const from paired vector store builtins

Author: Nemanja Ivanovic Date: 2022-05-31T21:51:15-05:00 New Revision: 1013967436694f362097a7c12f675c0ad7de90b7 URL: https://github.com/llvm/llvm-project/commit/1013967436694f362097a7c12f675c0ad7de90b7 DIFF:

[clang] dc1aa8e - [PowerPC] Add missed clang portion of c933c2eb3346

Author: Nemanja Ivanovic Date: 2021-11-24T12:42:58-06:00 New Revision: dc1aa8eacd1e0e554f206cc15d730f37ea90c4ea URL: https://github.com/llvm/llvm-project/commit/dc1aa8eacd1e0e554f206cc15d730f37ea90c4ea DIFF:

[clang] b7bf937 - [PowerPC] Provide XL-compatible vec_round implementation

Author: Nemanja Ivanovic Date: 2021-11-24T06:43:56-06:00 New Revision: b7bf937bbee38c2db0c0640176ef618d9c746538 URL: https://github.com/llvm/llvm-project/commit/b7bf937bbee38c2db0c0640176ef618d9c746538 DIFF:

[clang] 369d785 - [PowerPC] Optimal sequence for doubleword vec_all_{eq|ne} on Power7

Author: Nemanja Ivanovic Date: 2021-10-01T08:27:15-05:00 New Revision: 369d785574f5a22c086d0c40268a39a64bdd7217 URL: https://github.com/llvm/llvm-project/commit/369d785574f5a22c086d0c40268a39a64bdd7217 DIFF:

[clang] fad14a1 - [PowerPC] Truncate element index for vec_insert in altivec.h

Author: Nemanja Ivanovic Date: 2021-09-30T05:58:22-05:00 New Revision: fad14a17a490b1825b0c7c40ace7e83c91af4b8a URL: https://github.com/llvm/llvm-project/commit/fad14a17a490b1825b0c7c40ace7e83c91af4b8a DIFF:

[clang] 09b67aa - [PowerPC] Implement builtin for vbpermd

Author: Nemanja Ivanovic Date: 2021-09-29T06:34:31-05:00 New Revision: 09b67aa1c38279daa54246e3f216186e35a3e5b9 URL: https://github.com/llvm/llvm-project/commit/09b67aa1c38279daa54246e3f216186e35a3e5b9 DIFF:

[clang] c9539f9 - [PowerPC] Define XL-compatible macros only for AIX and Linux

Author: Nemanja Ivanovic Date: 2021-09-29T06:14:45-05:00 New Revision: c9539f957f57c0c2c59dab98f25215f241d4debf URL: https://github.com/llvm/llvm-project/commit/c9539f957f57c0c2c59dab98f25215f241d4debf DIFF:

[clang] 76d845c - [clang-format] Fix unittest failures with -Werror

Author: Nemanja Ivanovic Date: 2021-09-23T18:24:39-05:00 New Revision: 76d845cb169f048cb6f2176c3e7a6534dc5af097 URL: https://github.com/llvm/llvm-project/commit/76d845cb169f048cb6f2176c3e7a6534dc5af097 DIFF:

[clang] 9019b55 - [PowerPC] Fix byte ordering of ld/st with length on BE

Author: Nemanja Ivanovic Date: 2021-07-30T14:37:24-05:00 New Revision: 9019b55b605a26cb5389399eceb34fa9ea0f URL: https://github.com/llvm/llvm-project/commit/9019b55b605a26cb5389399eceb34fa9ea0f DIFF:

[clang] 84e4296 - [PowerPC] Fix rounding mode for vec_round in altivec.h

Author: Nemanja Ivanovic Date: 2021-07-12T06:11:27-05:00 New Revision: 84e429693fe5f225fe68b9dd54043cddb9c4cd4c URL: https://github.com/llvm/llvm-project/commit/84e429693fe5f225fe68b9dd54043cddb9c4cd4c DIFF:

[clang] 41ce5ec - [PowerPC] Remove unnecessary 64-bit guards from altivec.h

Author: Nemanja Ivanovic Date: 2021-07-12T04:59:00-05:00 New Revision: 41ce5ec5f6f3a03d70e0010e3a140fe129800637 URL: https://github.com/llvm/llvm-project/commit/41ce5ec5f6f3a03d70e0010e3a140fe129800637 DIFF:

[clang] ef90657 - [PowerPC] Fix vec_add for 64-bit on pre-Power7 subtargets

Author: Nemanja Ivanovic Date: 2021-06-24T18:42:44-05:00 New Revision: ef906573a127cffef7cae75d5155c15a8a2a3a5e URL: https://github.com/llvm/llvm-project/commit/ef906573a127cffef7cae75d5155c15a8a2a3a5e DIFF:

[clang] 7cd2833 - [PowerPC] Add vec_vupkhpx and vec_vupklpx for XL compatibility

Author: Nemanja Ivanovic Date: 2021-05-14T08:02:00-05:00 New Revision: 7cd2833311ab614775bc695e7bb808159a02e2a9 URL: https://github.com/llvm/llvm-project/commit/7cd2833311ab614775bc695e7bb808159a02e2a9 DIFF:

[clang] 39e4676 - [PowerPC] Provide doubleword vector predicate form comparisons on Power7

Author: Nemanja Ivanovic Date: 2021-05-13T04:56:56-05:00 New Revision: 39e4676ca798d9aba58823515ac9d48eb64863be URL: https://github.com/llvm/llvm-project/commit/39e4676ca798d9aba58823515ac9d48eb64863be DIFF:

Re: [clang] ed87f51 - [PowerPC] Provide some P8-specific altivec overloads for P7

now. > > On Thu, May 6, 2021 at 9:58 AM Nico Weber wrote: > >> Looks like this breaks tests: http://45.33.8.238/linux/45985/step_7.txt >> , https://lab.llvm.org/buildbot/#/builders/139/builds/3818 >> >> (Is there a phab link for this?) >> >> On Thu, May 6,

[clang] 1faf3b1 - [PowerPC] Re-commit ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8

Author: Nemanja Ivanovic Date: 2021-05-06T09:50:12-05:00 New Revision: 1faf3b195e71dbc469d658d450949439dbf92f9f URL: https://github.com/llvm/llvm-project/commit/1faf3b195e71dbc469d658d450949439dbf92f9f DIFF:

[clang] ed87f51 - [PowerPC] Provide some P8-specific altivec overloads for P7

Author: Nemanja Ivanovic Date: 2021-05-06T08:37:36-05:00 New Revision: ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8 URL: https://github.com/llvm/llvm-project/commit/ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8 DIFF:

[clang] bfd60b3 - [PowerPC] Add floating point overloads for vec_sldw

Author: Nemanja Ivanovic Date: 2021-04-30T20:29:03-05:00 New Revision: bfd60b36f825c299971bb0c2bf973031e2e0fc09 URL: https://github.com/llvm/llvm-project/commit/bfd60b36f825c299971bb0c2bf973031e2e0fc09 DIFF:

[clang] c3da07d - [PowerPC] Provide fastmath sqrt and div functions in altivec.h

Author: Nemanja Ivanovic Date: 2021-04-30T19:17:48-05:00 New Revision: c3da07d216dd20fbdb7302fd085c0a59e189ae3d URL: https://github.com/llvm/llvm-project/commit/c3da07d216dd20fbdb7302fd085c0a59e189ae3d DIFF:

[clang] 19b29b1 - [PowerPC] Provide XL-compatible builtins in altivec.h

Author: Nemanja Ivanovic Date: 2021-04-23T15:13:46-05:00 New Revision: 19b29b1ed1baa3c91a8e48204a8fb229bf07f548 URL: https://github.com/llvm/llvm-project/commit/19b29b1ed1baa3c91a8e48204a8fb229bf07f548 DIFF:

[clang] 6725b90 - [PowerPC] Add vec_ctsl and vec_ctul to altivec.h

Author: Nemanja Ivanovic Date: 2021-04-23T11:03:38-05:00 New Revision: 6725b90a02c6d2696385c0328bd000516913ce4b URL: https://github.com/llvm/llvm-project/commit/6725b90a02c6d2696385c0328bd000516913ce4b DIFF:

[clang] 1cc1d9d - [PowerPC] Add vec_vclz as an alias for vec_cntlz in altivec.h

Author: Nemanja Ivanovic Date: 2021-04-22T10:31:00-05:00 New Revision: 1cc1d9db286c7fbd0ff0a0757c2da2a5a6fc54a8 URL: https://github.com/llvm/llvm-project/commit/1cc1d9db286c7fbd0ff0a0757c2da2a5a6fc54a8 DIFF:

[clang] 7a5641d - [PowerPC] Add missing casts for vec_xlds and vec_load_splats

Author: Nemanja Ivanovic Date: 2021-04-22T10:31:00-05:00 New Revision: 7a5641d651963e91b05f25667df6cc694503248f URL: https://github.com/llvm/llvm-project/commit/7a5641d651963e91b05f25667df6cc694503248f DIFF:

[clang] e43963d - [PowerPC] Add vec_load_splats to altivec.h

Author: Nemanja Ivanovic Date: 2021-04-22T10:31:00-05:00 New Revision: e43963db24f68582edba8b227432714c60eac0c9 URL: https://github.com/llvm/llvm-project/commit/e43963db24f68582edba8b227432714c60eac0c9 DIFF:

[clang] a0e6189 - [PowerPC] Add vec_xlds to altivec.h

Author: Nemanja Ivanovic Date: 2021-04-22T10:31:00-05:00 New Revision: a0e6189712297fd9a25723384039418bc68e8e9f URL: https://github.com/llvm/llvm-project/commit/a0e6189712297fd9a25723384039418bc68e8e9f DIFF:

[clang] a1d325a - [PowerPC] Add vec_roundz as alias for vec_trunc in altivec.h

Author: Nemanja Ivanovic Date: 2021-04-22T10:31:00-05:00 New Revision: a1d325af6708ebd8ac9efb8d2d148f16feeda3fd URL: https://github.com/llvm/llvm-project/commit/a1d325af6708ebd8ac9efb8d2d148f16feeda3fd DIFF:

[clang] 1550c47 - [PowerPC] Add vec_roundp as alias for vec_ceil

Author: Nemanja Ivanovic Date: 2021-04-22T10:30:59-05:00 New Revision: 1550c47c18f05800b20af071da50881ffd996254 URL: https://github.com/llvm/llvm-project/commit/1550c47c18f05800b20af071da50881ffd996254 DIFF:

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