https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/109420
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@@ -953,9 +953,20 @@ Intrinsic::Intrinsic(StringRef Name, StringRef Proto,
uint64_t MergeTy,
SVEEmitter &Emitter, StringRef SVEGuard,
StringRef SMEGuard)
: Name(Name.str()), LLVMName(LLVMName), Proto(Proto.str()),
- BaseTypeSp
@@ -1003,6 +998,13 @@ defm SVFCVT_F32_F64 : SInstCvtMXZ<"svcvt_f32[_f64]",
"MMPd", "MPd", "d", "aarc
defm SVFCVT_F64_F16 : SInstCvtMXZ<"svcvt_f64[_f16]", "ddPO", "dPO", "d",
"aarch64_sve_fcvt_f64f16">;
defm SVFCVT_F64_F32 : SInstCvtMXZ<"svcvt_f64[_f32]", "ddPM", "dPM", "
@@ -5553,6 +5553,14 @@ static SDValue getSVEPredicateBitCast(EVT VT, SDValue
Op, SelectionDAG &DAG) {
if (InVT == VT)
return Op;
+ // Look through casts to when their input has more lanes than
paulwalker-arm wrote:
Done, plus removed another redundan
@@ -4072,6 +4078,30 @@ static Value *upgradeX86IntrinsicCall(StringRef Name,
CallBase *CI, Function *F,
return Rep;
}
+static Value *upgradeAArch64IntrinsicCall(StringRef Name, CallBase *CI,
+ Function *F, IRBuilder<> &Builder) {
+
https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/110281
>From 7fd66c7630ec03db05203c7ffdf8e36e23e30d93 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Thu, 26 Sep 2024 18:07:52 +0100
Subject: [PATCH 1/2] [AArch64][SVE] Fix definition of bfloat fcvt intrinsics
@@ -5553,6 +5553,14 @@ static SDValue getSVEPredicateBitCast(EVT VT, SDValue
Op, SelectionDAG &DAG) {
if (InVT == VT)
return Op;
+ // Look through casts to when their input has more lanes than
+ // VT. This will increase the chances of removing casts that introduce n
@@ -5553,6 +5553,14 @@ static SDValue getSVEPredicateBitCast(EVT VT, SDValue
Op, SelectionDAG &DAG) {
if (InVT == VT)
return Op;
+ // Look through casts to when their input has more lanes than
paulwalker-arm wrote:
I knew something was odd when I was
https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/110281
Affected intrinsics:
llvm.aarch64.sve.fcvt.bf16f32
llvm.aarch64.sve.fcvtnt.bf16f32
The named intrinsics took a predicate based on the smallest element type when
it should be based on the largest.
https://github.com/paulwalker-arm closed
https://github.com/llvm/llvm-project/pull/109423
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@@ -2986,6 +2986,14 @@ void CastOperation::CheckCStyleCast() {
return;
}
+ if ((DestType->isArmMFloat8Type() && !SrcType->isArmMFloat8Type()) ||
+ (!DestType->isArmMFloat8Type() && SrcType->isArmMFloat8Type())) {
paulwalker-arm wrote:
`DestType->i
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/97277
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@@ -2644,6 +2644,8 @@ class alignas(TypeAlignment) Type : public
ExtQualsTypeCommonBase {
bool isQueueT() const;// OpenCL queue_t
bool isReserveIDT() const;// OpenCL reserve_id_t
+ bool isArmMFloat8Type() const; // AARCH64_OPAQ
@@ -3437,9 +3446,19 @@ StringRef BuiltinType::getName(const PrintingPolicy
&Policy) const {
case Id: \
return #ExtType;
#include "clang/Basic/OpenCLExtensionTypes.def"
-#define SVE_TYPE(Name, Id, SingletonId) \
- case Id: \
+#define SVE_VECTOR_TYPE(Name, MangledName, Id
@@ -97,6 +97,12 @@
SVE_TYPE(Name, Id, SingletonId)
#endif
+#ifndef AARCH64_OPAQUE_TYPE
+#define AARCH64_OPAQUE_TYPE(Name, MangledName, Id, SingletonId, NumEls, \
+ElBits, NF) \
+ SVE_TYPE(Name, Id, SingletonId)
+#endif
+
paulwalk
@@ -782,6 +782,13 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType
*BT) {
#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
#include "clang/Basic/AArch64SVEACLETypes.def"
{
+ if (BT->getKind() == BuiltinType::ArmMFloat8) {
+Encoding = llv
@@ -325,6 +325,8 @@ class DeclSpec {
#define HLSL_INTANGIBLE_TYPE(Name, Id, SingletonId)
\
static const TST TST_##Name = clang::TST_##Name;
#include "clang/Basic/HLSLIntangibleTypes.def"
+ // AARCH64_OPAQUE_TYPE
+ static const TST TST_ArmMFloat8_
@@ -2218,6 +2219,12 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T)
const {
Width = 0;
\
Align = 16;
\
break;
+#define AARCH64_OP
https://github.com/paulwalker-arm commented:
Sorry, my comments are a bit all over the place, but I'm concerned we've not
defined enough (and/or I need to understand what it means to be a storage only
type) for me to confidently accept this PR.
If possible, my suggestion is to detach the scala
@@ -1802,9 +1854,29 @@ void SVEEmitter::createStreamingAttrs(raw_ostream &OS,
ACLEKind Kind) {
if (Def->isFlagSet(IsStreamingFlag))
StreamingMap["ArmStreaming"].insert(Def->getMangledName());
-else if (Def->isFlagSet(VerifyRuntimeMode))
+else if (Def->isFlag
@@ -1802,9 +1854,29 @@ void SVEEmitter::createStreamingAttrs(raw_ostream &OS,
ACLEKind Kind) {
if (Def->isFlagSet(IsStreamingFlag))
StreamingMap["ArmStreaming"].insert(Def->getMangledName());
-else if (Def->isFlagSet(VerifyRuntimeMode))
+else if (Def->isFlag
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/109263
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https://github.com/paulwalker-arm approved this pull request.
Whilst I understand the rational for requesting an alternate solution, it feels
unfair. If the PR was to add a new OS or Vendor I'd have more sympathy but
here we're talking about extending the existing OS-Vendor support to cover
a
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@@ -567,23 +567,28 @@ static bool checkArmStreamingBuiltin(Sema &S, CallExpr
*TheCall,
// * When compiling for SVE only, the caller must be in non-streaming mode.
// * When compiling for both SVE and SME, the caller can be in either mode.
if (BuiltinType == SemaARM::Veri
https://github.com/paulwalker-arm closed
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paulwalker-arm wrote:
I'll need to look to see if the TBAA metadata we're adding matches what we
initially envisaged but my gut feeling matches @arsenm.
I'm assuming the original code emitted an error, something along the lines of
"no version of svst1 available for long long*", which you've "f
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>From 05670ea720be07ff8c1645ca90fff00460029de7 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Fri, 6 Sep 2024 12:10:19 +0100
Subject: [PATCH] [NFC][Clang][SVE] Refactor AArch64SVEACLETypes.def to enable
https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/107599
Some switch statements require all SVE builtin types to be manually specified.
This patch refactors the SVE_*_TYPE macros so that such code can be generated
during preprocessing.
I've tried to establish
@@ -717,6 +717,11 @@ let Predicates = [HasSVEorSME] in {
defm FDIV_ZPZZ : sve_fp_bin_pred_hfd;
} // End HasSVEorSME
+let Predicates = [HasSVE2orSME2, HasFAMINMAX] in {
+ defm FAMAX_ZPZZ : sve_fp_bin_pred_hfd;
+ defm FAMIN_ZPZZ : sve_fp_bin_pred_hfd;
+}
+
@@ -0,0 +1,115 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mattr=+sve2 < %s | FileCheck %s
+; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s
+
+target triple = "aarch64-linux"
+
+define @famin_f
https://github.com/paulwalker-arm approved this pull request.
A couple of suggestions but otherwise this looks good to me.
https://github.com/llvm/llvm-project/pull/99042
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@@ -135,6 +135,8 @@ enum NodeType : unsigned {
UDIV_PRED,
UMAX_PRED,
UMIN_PRED,
+ FAMAX_PRED,
+ FAMIN_PRED,
paulwalker-arm wrote:
Yep, the latter. We use it here because the ISD node exists for other reasons
and so was convenient to reuse here.
In ge
@@ -135,6 +135,8 @@ enum NodeType : unsigned {
UDIV_PRED,
UMAX_PRED,
UMIN_PRED,
+ FAMAX_PRED,
+ FAMIN_PRED,
paulwalker-arm wrote:
Is it necessary to create dedicated AArch64ISD nodes? We normally reserve that
for cases where additional DAG combines ar
paulwalker-arm wrote:
Just to add the commit message needs updating to reflect the updated
specification.
https://github.com/llvm/llvm-project/pull/97277
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@@ -3197,6 +3197,13 @@ void CastOperation::CheckCStyleCast() {
}
}
+ if ((DestType->isMFloat8Type() && !SrcType->isMFloat8Type()) ||
+ (!DestType->isMFloat8Type() && SrcType->isMFloat8Type())) {
paulwalker-arm wrote:
`DestType->isMFloat8Type() !=
@@ -1139,6 +1139,7 @@ class ASTContext : public RefCountedBase {
CanQualType SatShortFractTy, SatFractTy, SatLongFractTy;
CanQualType SatUnsignedShortFractTy, SatUnsignedFractTy,
SatUnsignedLongFractTy;
+ CanQualType MFloat8Ty;
paulwalker-arm wrote:
@@ -221,6 +221,10 @@ FLOATING_TYPE(Float128, Float128Ty)
// '__ibm128'
FLOATING_TYPE(Ibm128, Ibm128Ty)
+
+// '__fpm8'
paulwalker-arm wrote:
__mfp8
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paulwalker-arm wrote:
Sorry for the noise but I think I've a more wellformed question this time.
Is it be possible to use `AArch64SVEACLETypes.def` to reduce some of the
boilerplate changes? I'm not sure how much of this is tied to SVE (or rather
scalable types) but I'm wondering if clang can
paulwalker-arm wrote:
Is it possible to use TargetExtType for the scalar type given this is a target
specific type. I fully expect LLVM not to support vector's of TargetExtType
but I wonder if that can be relaxed given our only use case is to pass them to
intrinsics. For anything more exotic
https://github.com/paulwalker-arm approved this pull request.
This is certainly a step in the right direction.
https://github.com/llvm/llvm-project/pull/96482
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@@ -1781,7 +1781,13 @@ void SVEEmitter::createStreamingAttrs(raw_ostream &OS,
ACLEKind Kind) {
uint64_t VerifyRuntimeMode = getEnumValueForFlag("VerifyRuntimeMode");
uint64_t IsStreamingCompatibleFlag =
getEnumValueForFlag("IsStreamingCompatible");
+
for (auto &De
@@ -2264,6 +2278,18 @@ let TargetGuard = "sve2p1" in {
defm SVPMOV_TO_VEC_LANE_D : PMOV_TO_VEC<"svpmov", "lUl",
"aarch64_sve_pmov_to_vector_lane" ,[], ImmCheck1_7>;
}
+let TargetGuard = "sve2p1|sme2p1" in {
+ // DUPQ
+ def SVDUP_LANEQ_B : SInst<"svdup_laneq[_{d}]", "ddi"
https://github.com/paulwalker-arm commented:
With the change of default it's very hard to check everything but we've already
agreed there'll need to be a full audit once all the inflight work has landed.
I did spot one thing though:
Should the integer svclamp and svrevd builtins be protected
@@ -286,17 +290,20 @@ let TargetGuard = "sve,f64mm,bf16" in {
}
let TargetGuard = "sve,bf16" in {
+ def SVBFMMLA : SInst<"svbfmmla[_{0}]", "MMdd", "b", MergeNone,
"aarch64_sve_bfmmla", [IsOverloadNone]>;
+}
+
+let TargetGuard = "(sve|sme),bf16" in {
def
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@@ -17,7 +25,7 @@
// CPP-CHECK-NEXT:[[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 4
// CPP-CHECK-NEXT:ret i64 [[TMP1]]
//
-uint64_t test_svcntb()
+uint64_t test_svcntb(void) MODE_ATTR
paulwalker-arm wrote:
Is there a problem we need to worry about with usin
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@@ -286,10 +290,13 @@ let TargetGuard = "sve,f64mm,bf16" in {
}
let TargetGuard = "sve,bf16" in {
+ def SVBFMMLA : SInst<"svbfmmla[_{0}]", "MMdd", "b", MergeNone,
"aarch64_sve_bfmmla", [IsOverloadNone]>;
+}
+
+let TargetGuard = "(sve,bf16)|sme" in {
--
@@ -1781,7 +1781,12 @@ void SVEEmitter::createStreamingAttrs(raw_ostream &OS,
ACLEKind Kind) {
uint64_t VerifyRuntimeMode = getEnumValueForFlag("VerifyRuntimeMode");
uint64_t IsStreamingCompatibleFlag =
getEnumValueForFlag("IsStreamingCompatible");
+
for (auto &De
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@@ -2264,6 +2278,18 @@ let TargetGuard = "sve2p1" in {
defm SVPMOV_TO_VEC_LANE_D : PMOV_TO_VEC<"svpmov", "lUl",
"aarch64_sve_pmov_to_vector_lane" ,[], ImmCheck1_7>;
}
+let TargetGuard = "sve2p1|sme2" in {
paulwalker-arm wrote:
I think this is a sme2p1 feat
https://github.com/paulwalker-arm commented:
Not for this patch but I do wonder if there's value in protecting non-bf16
instruction backed builtins (e.g. loadstone and shuffles) with the bf16 target
guard. I figure we'll either error on the use of the `svbfloat` type or the
code generation sh
https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/93802
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@@ -559,31 +559,76 @@ SemaARM::ArmStreamingType getArmStreamingFnType(const
FunctionDecl *FD) {
return SemaARM::ArmNonStreaming;
}
-static void checkArmStreamingBuiltin(Sema &S, CallExpr *TheCall,
- const FunctionDecl *FD,
-
@@ -622,7 +679,8 @@ bool SemaARM::CheckSMEBuiltinFunctionCall(unsigned
BuiltinID,
}
if (BuiltinType)
- checkArmStreamingBuiltin(SemaRef, TheCall, FD, *BuiltinType);
+ HasError |= checkArmStreamingBuiltin(SemaRef, TheCall, FD, *BuiltinType,
p
@@ -559,31 +559,86 @@ SemaARM::ArmStreamingType getArmStreamingFnType(const
FunctionDecl *FD) {
return SemaARM::ArmNonStreaming;
}
-static void checkArmStreamingBuiltin(Sema &S, CallExpr *TheCall,
- const FunctionDecl *FD,
-
@@ -559,31 +559,86 @@ SemaARM::ArmStreamingType getArmStreamingFnType(const
FunctionDecl *FD) {
return SemaARM::ArmNonStreaming;
}
-static void checkArmStreamingBuiltin(Sema &S, CallExpr *TheCall,
- const FunctionDecl *FD,
-
paulwalker-arm wrote:
@momchil-velikov's commentary applies globally and is not specific to FPMR.
Which is to say, Arm switched a while back from "all system register need to be
protected by their feature flag" to "only protect system registers where there
is a need". The rational is that we
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@@ -561,16 +561,61 @@ SemaARM::ArmStreamingType getArmStreamingFnType(const
FunctionDecl *FD) {
static void checkArmStreamingBuiltin(Sema &S, CallExpr *TheCall,
const FunctionDecl *FD,
- SemaARM::ArmStre
@@ -225,7 +225,7 @@ def IsStreamingCompatible :
FlagType<0x40>;
def IsReadZA: FlagType<0x80>;
def IsWriteZA : FlagType<0x100>;
def IsReductionQV : FlagType<0x200>;
-def Is
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https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/92427
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https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/91356
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https://github.com/paulwalker-arm commented:
After further discussion I know understand the `__arm_streaming_compatible`
keyword has no affect on the target features in play and only tells the
compiler not to emit any SM state changing instructions as part of the calling
convention.
https://g
@@ -8982,11 +8982,18 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD)
{
const FunctionDecl *FD = cast(CurContext);
llvm::StringMap CallerFeatureMap;
Context.getFunctionFeatureMap(CallerFeatureMap, FD);
-if (!Builtin::evaluateRequiredTargetFeatures(
-
@@ -9,6 +9,12 @@
#include
+#if defined __ARM_FEATURE_SME
+#define MODE_ATTR __arm_streaming
+#else
+#define MODE_ATTR __arm_streaming_compatible
paulwalker-arm wrote:
Do you need to use `__arm_streaming_compatible` here? Now we've agreed this
keyword has
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https://github.com/paulwalker-arm requested changes to this pull request.
As discussed offline, I don't think we want to be this strict. As demonstrated
by the changes to the ACLE tests, this change makes it impossible to distribute
a library in binary form that can work for both SVE and InStr
https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/88748
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https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/89762
We only use common intrinsics for operations that treat their element type as a
container of bits.
>From ed27a2d1406dccf70e7189578cd6950b61961c1b Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Tue, 23
https://github.com/paulwalker-arm closed
https://github.com/llvm/llvm-project/pull/82810
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>From a4c46459564bd8a8e5ca2a56fa643f866b7e869a Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Fri, 23 Feb 2024 18:26:10 +
Subject: [PATCH] [LLVM][TypeSize] Remove default constructor.
---
clang/lib
https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/82810
Implements the follow-on work requesting on
https://github.com/llvm/llvm-project/pull/75614.
>From a75304dffb77be1fb15f268000bfbdd07be774e1 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Fri, 23 Feb 20
@@ -10570,6 +10570,26 @@ Value
*CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return Builder.CreateCall(F, llvm::ConstantInt::get(Int32Ty, HintID));
}
+ if (BuiltinID == clang::AArch64::BI__builtin_arm_get_sme_state) {
+// Create call to __arm_sme_sta
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/75791
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https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/75791
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@@ -1600,6 +1600,25 @@ void SVEEmitter::createSMEHeader(raw_ostream &OS) {
OS << "extern \"C\" {\n";
OS << "#endif\n\n";
+ OS << "void __arm_za_disable(void) __arm_streaming_compatible;\n\n";
+
+ OS << "__ai bool __arm_has_sme(void) __arm_streaming_compatible {\n";
+ OS
@@ -10570,6 +10570,26 @@ Value
*CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return Builder.CreateCall(F, llvm::ConstantInt::get(Int32Ty, HintID));
}
+ if (BuiltinID == clang::AArch64::BI__builtin_arm_get_sme_state) {
+// Create call to __arm_sme_sta
@@ -10570,6 +10570,26 @@ Value
*CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
return Builder.CreateCall(F, llvm::ConstantInt::get(Int32Ty, HintID));
}
+ if (BuiltinID == clang::AArch64::BI__builtin_arm_get_sme_state) {
+// Create call to __arm_sme_sta
@@ -1600,6 +1600,25 @@ void SVEEmitter::createSMEHeader(raw_ostream &OS) {
OS << "extern \"C\" {\n";
OS << "#endif\n\n";
+ OS << "void __arm_za_disable(void) __arm_streaming_compatible;\n\n";
+
+ OS << "__ai bool __arm_has_sme(void) __arm_streaming_compatible {\n";
+ OS
https://github.com/paulwalker-arm closed
https://github.com/llvm/llvm-project/pull/75217
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paulwalker-arm wrote:
Turns out there was just a single extra instance, within MLIR. It's an
interesting one though and I've noted it as it looks like I'll need to extend
`ModuleImport::getConstantAsAttr` as part of the patch that enables direct
VectorType support for ConstantInt/FP.
https:/
https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/75217
>From d19e9e20432c0dfe50bfba7cd782179653f42b2b Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Wed, 29 Nov 2023 14:45:06 +
Subject: [PATCH] [LLVM][IR] Replace ConstantInt's specialisation of getType()
paulwalker-arm wrote:
Just a note to say the PR is not complete because there are uses outside of
clang and llvm that I need to port.
https://github.com/llvm/llvm-project/pull/75217
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https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/75217
>From b484b3c60b172fadb6fa600cdc15a865750867a8 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Wed, 29 Nov 2023 14:45:06 +
Subject: [PATCH] [LLVM][IR] Replace ConstantInt's specialisation of getType()
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