https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/156047
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@@ -4148,6 +4148,34 @@ static Value *upgradeX86IntrinsicCall(StringRef Name,
CallBase *CI, Function *F,
Value *Args[] = {CI->getArgOperand(0), CI->getArgOperand(1),
CI->getArgOperand(2)};
+
+// Input arguments types were incorrectly set to vectors
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/155199
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@@ -40,16 +40,16 @@ _mm_macc_pd(__m128d __A, __m128d __B, __m128d __C) {
(__v2df)__C);
}
-static __inline__ __m128 __DEFAULT_FN_ATTRS128
+static __inline__ __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_macc_ss(__m128 __A, __m128 __B, _
phoebewang wrote:
> > Convert _mm_lzcnt_epi32 etc. (inc mask/maskz variants) to use
> > __builtin_elementwise_ctlz
>
> It's not obvious to me how the mask/maskz variants (e.g.
> `_mm_maskz_lzcnt_epi32`) can be refactored to use
> `__builtin_elementwise_ctlz`.
>
> Is it enough to replace this
@@ -42,35 +43,41 @@ __m512i test_mm512_maskz_conflict_epi32(__mmask16 __U,
__m512i __A) {
}
__m512i test_mm512_lzcnt_epi32(__m512i __A) {
// CHECK-LABEL: test_mm512_lzcnt_epi32
- // CHECK: call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %{{.*}}, i1 false)
+ // CHECK: call <16
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LGTM.
https://github.com/llvm/llvm-project/pull/154737
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phoebewang wrote:
We don't guarantee builtins compatibility. You should use intrinsic
`_mm256_mask_cvtph_ps` instead. Please taking care of the difference in
arguments order.
https://github.com/llvm/llvm-project/pull/152911
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/154558
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/154341
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/152705
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/153293
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@@ -389,6 +389,7 @@ __m64 test_mm_mul_su32(__m64 a, __m64 b) {
// CHECK: mul <2 x i64> %{{.*}}, %{{.*}}
return _mm_mul_su32(a, b);
}
+TEST_CONSTEXPR(match_m64(_mm_mul_su32((__m64)(__v4hi){+1, -2, +3, -4},
(__m64)(__v4hi){-10, +8, +6, -4}), 2533154533212150));
-
phoebewang wrote:
> "CF" is a hardware feature; it's incredibly confusing to just pretend it
> doesn't exist because it's slow. If you need to adjust codegen, add a
> separate feature TuningSlowCF or something.
Although it's a hardware feature, it's fully under software control due to it's
au
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/153820
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@@ -389,6 +389,7 @@ __m64 test_mm_mul_su32(__m64 a, __m64 b) {
// CHECK: mul <2 x i64> %{{.*}}, %{{.*}}
return _mm_mul_su32(a, b);
}
+TEST_CONSTEXPR(match_m64(_mm_mul_su32((__m64)(__v4hi){+1, -2, +3, -4},
(__m64)(__v4hi){-10, +8, +6, -4}), 2533154533212150));
-
@@ -344,6 +344,7 @@ __m128i test_mm_mul_epi32(__m128i x, __m128i y) {
// CHECK: mul <2 x i64> %{{.*}}, %{{.*}}
return _mm_mul_epi32(x, y);
}
+TEST_CONSTEXPR(match_m128i(_mm_mul_epi32((__m128i)(__v8hi){+1, -2, +3, -4, +5,
-6, +7, -8}, (__m128i)(__v8hi){-16, -14, +12, +10, -
@@ -925,6 +925,7 @@ __m128i test_mm_mul_epu32(__m128i A, __m128i B) {
// CHECK: mul <2 x i64> %{{.*}}, %{{.*}}
return _mm_mul_epu32(A, B);
}
+TEST_CONSTEXPR(match_m128i(_mm_mul_epu32((__m128i)(__v8hi){+1, -2, +3, -4, +5,
-6, +7, -8}, (__m128i)(__v8hi){-16, -14, +12, +10, -
@@ -389,6 +389,7 @@ __m64 test_mm_mul_su32(__m64 a, __m64 b) {
// CHECK: mul <2 x i64> %{{.*}}, %{{.*}}
return _mm_mul_su32(a, b);
}
+TEST_CONSTEXPR(match_m64(_mm_mul_su32((__m64)(__v4hi){+1, -2, +3, -4},
(__m64)(__v4hi){-10, +8, +6, -4}), 2533154533212150));
-
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/153820
They are defined in mmintrin.h
>From 56358bd19058486ed7b4e19c43255199ffb1ccd0 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 15 Aug 2025 23:33:23 +0800
Subject: [PATCH] [Headers][X86] Remove more d
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/153734
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phoebewang wrote:
> Update description?
>
> Due to it results in more losses than gains. -> Due to it results in more
> losses than gains w/o HWPGO.
I assume HWPGO is not mature enough.
https://github.com/llvm/llvm-project/pull/153751
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https://github.com/llvm/llvm-project/pull/153751
Due to it results in more losses than gains.
>From 155a039f02a9dcabeae70ac4ff9438bdc3357d41 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 15 Aug 2025 14:18:20 +0800
Subject: [PATCH] [X86][APX] Rem
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/153734
Newly added in xmmintrin.h by c8312bdd1665225c585dd2b0bff5e46d569edd45
>From 40265a5b25d3bed04e99532b7202945f08c95dd8 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 15 Aug 2025 11:28:07 +0800
Subje
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/153433
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@@ -1,11 +1,11 @@
-// RUN: %clang_cc1 %s -emit-llvm -o -
+// RUN: %clang_cc1 %s -emit-llvm -flax-vector-conversions=none -o -
typedef float __m128 __attribute__((__vector_size__(16)));
typedef long long __v2di __attribute__((__vector_size__(16)));
typedef int __v4si __attrib
@@ -1,16 +1,16 @@
// REQUIRES: x86-registered-target
-// RUN: %clang_cc1 %s -triple=i686-apple-darwin -target-feature +ssse3 -O1 -S
-o - | FileCheck %s
+// RUN: %clang_cc1 %s -triple=i686-apple-darwin -target-feature +ssse3 -O1 -S
-flax-vector-conversions=none -o - | FileCheck
@@ -56,11 +56,6 @@ namespace Vector {
static_assert(__builtin_vectorelements(v2) == (32 / sizeof(double)), "");
}
-namespace {
- typedef float __attribute__((vector_size(16))) VI42;
- constexpr VI42 A2 = A;
phoebewang wrote:
Can we change it to `A2 = {1.f
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/152971
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@@ -40,12 +40,17 @@ typedef signed char __v16qs
__attribute__((__vector_size__(16)));
#ifdef __SSE2__
/* Both _Float16 and __bf16 require SSE2 being enabled. */
+typedef _Float16 __v4hf __attribute__((__vector_size__(8)));
typedef _Float16 __v8hf __attribute__((__vector_size
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/152701
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LGTM.
https://github.com/llvm/llvm-project/pull/152545
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@@ -940,18 +940,21 @@ __m128i test_mm_mulhi_epi16(__m128i A, __m128i B) {
// CHECK: call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %{{.*}}, <8 x i16>
%{{.*}})
return _mm_mulhi_epi16(A, B);
}
+TEST_CONSTEXPR(match_v8hi(_mm_mulhi_epi16((__m128i)(__v8hi){+1, -2, +3, -4,
+5,
@@ -365,12 +365,14 @@ __m64 test_mm_mulhi_pi16(__m64 a, __m64 b) {
// CHECK: call <8 x i16> @llvm.x86.sse2.pmulh.w(
return _mm_mulhi_pi16(a, b);
}
+TEST_CONSTEXPR(match_v4hi(_mm_mulhi_pi16((__m64)(__v4hi){+1, -2, +3, -4},
(__m64)(__v4hi){-10, +8, +6, -4}), -1, -1, 0, 0));
@@ -11653,6 +11659,18 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr
*E) {
APSInt(LHS.isSigned() ? LHS.ssub_sat(RHS) : LHS.usub_sat(RHS),
DestEltTy->isUnsignedIntegerOrEnumerationType(;
break;
+ case clang::X86::BI__bu
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/152435
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/152305
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/152173
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phoebewang wrote:
Is the problem happening when enabling async-exceptions but not cxx-exceptions
on c++ objects? I'm not sure if it's a valid scenario. The designed requires
`cxx-exceptions`, see descriptions in
https://github.com/llvm/llvm-project/commit/797ad701522988e212495285dade8efac41a24
phoebewang wrote:
/cherry-pick
https://github.com/llvm/llvm-project/commit/3ea3e334cc19cdd34416b546ac4b4a24b2018a28
https://github.com/llvm/llvm-project/pull/151077
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phoebewang wrote:
The change needs a release note update, but I want to backport it to LLVM21
release. Would update LLVM21 release note instead.
https://github.com/llvm/llvm-project/pull/151077
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h
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/151077
For maskz intrinsics, the first argument is always the mask.
>From f175aa9a54b8fb6e3be91af0ae38e553a4d4852d Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Tue, 29 Jul 2025 10:59:38 +0800
Subject: [PATCH
phoebewang wrote:
> This requires a release note, especially because it fixes a bug.
We don't change the intrinsic behavior and bug fixes usually don't need a
release note. It's only needed when backporting to release branch.
https://github.com/llvm/llvm-project/pull/149745
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https://github.com/phoebewang approved this pull request.
https://github.com/llvm/llvm-project/pull/149745
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@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=i686-unknown-unknown
-target-feature +sm3 -fsyntax-only -verify
+
+#include
+
+__m128i test_mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C) {
+ return _mm_sm3rnds2_epi32(__A, __B, __C, 256); // expected-er
https://github.com/phoebewang requested changes to this pull request.
Please check test failures.
https://github.com/llvm/llvm-project/pull/149745
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@@ -14,3 +14,7 @@ void test_m_prefetch_it1(void *p) {
// CHECK-LABEL: define{{.*}} void @test_m_prefetch_it1
// CHECK: call void @llvm.prefetch.p0(ptr {{.*}}, i32 0, i32 2, i32 0)
}
+
+void test_invalid_prefetchi(void* p) {
+ return __builtin_ia32_prefetchi(p, 1); // expec
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/149745
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/149745
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phoebewang wrote:
Thanks for the patch! You can add a test case for it like
`clang/test/CodeGen/X86/sm3-error.c`
https://github.com/llvm/llvm-project/pull/149745
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@@ -176,10 +176,10 @@ constexpr FeatureBitset FeaturesArrowlakeS =
FeaturesArrowlake | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
FeatureSM4;
constexpr FeatureBitset FeaturesPantherlake =
-FeaturesArrowlakeS | FeaturePREFETCHI;
+FeaturesArrowlakeS ^ Feat
@@ -1056,4 +1056,62 @@ void SemaX86::handleForceAlignArgPointerAttr(Decl *D,
const ParsedAttr &AL) {
X86ForceAlignArgPointerAttr(getASTContext(), AL));
}
+enum FirstParam { Unsupported, Duplicate, Unknown };
+enum SecondParam { None, CPU, Tune };
+enum ThirdP
phoebewang wrote:
> TBH I'm not sure if we need to add `avx512f,evex512` to intrinsics attributes
> and/or to `.td` as well.
Yes, we need them for now. Otherwise, we cannot allocate ZMM registers.
https://github.com/llvm/llvm-project/pull/148633
___
@@ -16,7 +16,15 @@
#define __DEFAULT_FN_ATTRS_AVX512
\
__attribute__((__always_inline__, __nodebug__,
\
- __target__("amx-avx512,avx10.2-512")))
+ __target__("amx-avx
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/148184
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/148184
According to Intel [SDM088](https://cdrdv2.intel.com/v1/dl/getContent/671200)
Volume 1, Chapter 2.4, Key Locker will be removed from 2025 onwards products.
>From 9a8224c22535912a1fa95caa41f8fc2c3f7a76d0 Mon
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/144833
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/144833
>From 8e218d9c4431b021231942e514f175164af35a51 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Thu, 19 Jun 2025 12:14:54 +0800
Subject: [PATCH 1/2] [X86] Remove CLDEMOTE from Arrowlake and later hybrid
p
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/144833
Decouple Arrowlake from Sierraforest because the later has CLDEMOTE feature.
>From 8e218d9c4431b021231942e514f175164af35a51 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Thu, 19 Jun 2025 12:14:54 +0800
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/144662
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/144662
SDM doesn't list any hybrid processors in this feature. Besides, physical
machine also reports not supported.
>From 353fbfc93faa2c1bad26261b566d3f797b6d1a72 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Dat
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/141486
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https://github.com/phoebewang commented:
The pre-checkin failures seem related.
https://github.com/llvm/llvm-project/pull/138360
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@@ -138,6 +138,12 @@ let Attributes = [Const, NoThrow,
RequiredVectorWidth<256>], Features = "avx" in
}
}
+// PRFCHW
+let Features = "prfchw", Header = "intrin.h", Attributes = [NoThrow, Const] in
{
phoebewang wrote:
Although they are in the same file, bo
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/138360
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/136660
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@@ -0,0 +1,236 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,236 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,236 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -254,11 +256,20 @@ static bool CompressEVEXImpl(MachineInstr &MI, const
X86Subtarget &ST) {
}
}
+ bool IsWithReloc = false;
+ if (X86EnableAPXForRelocation) {
+int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) +
+ X86II::getOperandB
phoebewang wrote:
> This solution can not handle post-RA optimizations. Could we implement it in
> MC stage for this workaround?
We cannot change the register after RA. I don't see any problem for now expect
NF optimizations, which we can skip them for now.
https://github.com/llvm/llvm-projec
@@ -127,6 +127,7 @@
; CHECK-NEXT: X86 LEA Optimize
; CHECK-NEXT: X86 Optimize Call Frame
; CHECK-NEXT: X86 Avoid Store Forwarding Block
+; CHECK-NEXT: X86 Suppress APX features for relocation
phoebewang wrote:
Ok, we don't need to move
@@ -242,8 +244,18 @@ static EFLAGSClobber getClobberType(const MachineInstr
&MI) {
MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr);
if (!FlagDef)
return NoClobber;
- if (FlagDef->isDead() && X86::getNFVariant(MI.getOpcode()))
+
+ if (FlagDef->isDead() &&
https://github.com/phoebewang closed
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phoebewang wrote:
> > Any comments?
>
> Still not understand the requirement...
I'm confused by the test cases too. I understood the code as we replace the
EGPR or NDD instructions with non-APX ones, which meets my expection. But the
option and tests are in MC phase, which means instructions
@@ -0,0 +1,173 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,173 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,173 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -1,44 +1,84 @@
// REQUIRES: x86
-// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
+// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
-x86-apx-relax-relocations=true
// RUN: ld.lld %t.o -o %t1
// RUN: llvm-readobj -r %t1 | FileCheck -
@@ -912,9 +912,9 @@ void X86_64::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_X86_64_CODE_4_GOTPC32_TLSDESC:
case R_X86_64_TLSDESC_CALL:
case R_X86_64_TLSGD:
-if (rel.expr == R_RELAX_TLS_GD_TO_LE) {
+if (rel.expr == R_RELAX_TLS_GD_TO
@@ -0,0 +1,173 @@
+//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -89,6 +89,7 @@ set(sources
GISel/X86InstructionSelector.cpp
GISel/X86LegalizerInfo.cpp
GISel/X86RegisterBankInfo.cpp
+ X86SuppressAPXForReloc.cpp
phoebewang wrote:
Put it in alphabetic order?
https://github.com/llvm/llvm-project/pull/136660
@@ -912,9 +912,9 @@ void X86_64::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
case R_X86_64_CODE_4_GOTPC32_TLSDESC:
case R_X86_64_TLSDESC_CALL:
case R_X86_64_TLSGD:
-if (rel.expr == R_RELAX_TLS_GD_TO_LE) {
+if (rel.expr == R_RELAX_TLS_GD_TO
@@ -1,44 +1,84 @@
// REQUIRES: x86
-// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
+// RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
-x86-apx-relax-relocations=true
// RUN: ld.lld %t.o -o %t1
// RUN: llvm-readobj -r %t1 | FileCheck -
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/135489
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https://github.com/llvm/llvm-project/pull/135489
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phoebewang wrote:
/cherry-pick
https://github.com/llvm/llvm-project/commit/ebba554a3211b0b98d3ae33ba70f9d6ceaab6ad4
https://github.com/llvm/llvm-project/pull/135489
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/135489
According to SDM, they require both VAES/VPCLMULQDQ and AVX10.1 CPUID bits.
Fixes: #135394
>From f6c06c613a8b862307e643edb8f010cf2f666350 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sat, 12 Apr 2025
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/134528
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/134528
None
>From 04852072c016e6df3c9b6d834ba34c443593aa04 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sun, 6 Apr 2025 18:22:22 +0800
Subject: [PATCH] [X86][AVX10] Make warning message more informative, NFC
https://github.com/phoebewang edited
https://github.com/llvm/llvm-project/pull/131592
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/132397
Ref: https://cdrdv2.intel.com/v1/dl/getContent/784343
>From a8353b285f99b57a3d4ce28add512debc8761d5a Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Fri, 21 Mar 2025 20:54:06 +0800
Subject: [PATCH] [X86]
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/132414
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/134484
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/134484
Found by #64779.
>From b04e443d3569ec2ed352e127bf6fbfe0902b1ee1 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe"
Date: Sat, 5 Apr 2025 15:03:17 +0800
Subject: [PATCH] [X86][AMX] Add missing __inline__ for AMXCO
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/132397
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https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/134240
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