https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/152122
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LGTM
https://github.com/llvm/llvm-project/pull/153903
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@@ -71,21 +71,24 @@
// RUN: --check-prefixes=NO-FLAG,FUNC-SIG-SCHEME-UNUSED %s
// Default -mcf-branch-label-scheme is func-sig
-// RUN: %clang --target=riscv32 -fcf-protection=branch -S -emit-llvm %s -o - \
-// RUN: | FileCheck --check-prefixes=BRANCH-PROT-FLAG,FUNC-SIG-FLAG %
https://github.com/lenary commented:
Please can you add a LLVM IR test for `llc`?
I don't think I know enough about the "fixed vectors in scalable vectors"
lowering to know if `splitValueIntoRegisterParts` and
`joinRegisterPartsIntoValue` are correct but they don't seem so wrong at a
glance.
@@ -75,6 +75,8 @@ def riscv_sret_glue : RVSDNode<"SRET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
def riscv_mret_glue : RVSDNode<"MRET_GLUE", SDTNone,
[SDNPHasChain, SDNPOptInGlue]>;
+def riscv_mnret_glue : RVSD
@@ -22259,6 +22260,10 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
reportFatalUsageError(
"'SiFive-CLIC-*' interrupt kinds require XSfmclic extension");
+if (Kind == "rnmi" && !Subtarget.hasStdExtSmrnmi())
+ reportFatalUsageError("Handling of
https://github.com/lenary edited
https://github.com/llvm/llvm-project/pull/148134
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https://github.com/lenary commented:
The implementation here is good, and can be landed once there's a PR against
the riscv-c-api with some consensus. I don't think the chosen name will be
controversial.
https://github.com/llvm/llvm-project/pull/148134
_
lenary wrote:
This needs a proposal against the specification here:
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#__attribute__interrupt-__attribute__interruptsupervisor-__attribute__interruptmachine
https://github.com/llvm/llvm-project/pull/148134
__
@@ -599,11 +599,18 @@ void baremetal::Linker::ConstructJob(Compilation &C,
const JobAction &JA,
const Driver &D = getToolChain().getDriver();
const llvm::Triple::ArchType Arch = TC.getArch();
const llvm::Triple &Triple = getToolChain().getEffectiveTriple();
+ const bool
lenary wrote:
What is your intention here around the LLVM 21 release cycle, knowing this is a
big feature and we are 1 week from the branch date
https://github.com/llvm/llvm-project/pull/146534
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h
lenary wrote:
This seems to only implement the first bullet point in your commit message, and
assembler/relocation/fixup support, right? Please update the PR description.
I presume there will be follow-ups for the codegen/load-store support, plus
subtarget info.
https://github.com/llvm/llvm
@@ -790,6 +790,9 @@ static constexpr DecoderListEntry DecoderList32[]{
{DecoderTableXmipscmov32,
{RISCV::FeatureVendorXMIPSCMov},
"MIPS mips.ccmov"},
+{DecoderTableXmipscbop32,
+ {RISCV::FeatureVendorXMIPSCBOP},
+ "MIPS mips.pref"},
le
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LGTM
https://github.com/llvm/llvm-project/pull/145685
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@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs
< %s \
+; RUN: | FileCheck %s -check-prefix=RV32XMIPSPREFETCH
+; RUN: llc -mtriple=riscv64 -mattr=+xmip
@@ -190,6 +192,31 @@ insertWaveSizeFeature(StringRef GPU, const Triple &T,
StringMap &Features);
} // namespace AMDGPU
+
+struct BasicSubtargetFeatureKV {
+ const char *Key; ///< K-V key string
+ unsigned Value; ///< K-V integer value
+
@@ -190,6 +192,31 @@ insertWaveSizeFeature(StringRef GPU, const Triple &T,
StringMap &Features);
} // namespace AMDGPU
+
+struct BasicSubtargetFeatureKV {
+ const char *Key; ///< K-V key string
+ unsigned Value; ///< K-V integer value
+
lenary wrote:
Nice, I can navigate that UI.
Looks like a similar thing that I fixed-forward, but this time with a different
unwind library, but clang isn't very happy with mixing unwind libraries anyway.
I think I'll leave this to @quic-garvgupt to fix, using the info from your link.
https://
lenary wrote:
We probably need to file an infrastructure ticket to get to the bottom of this
issue. I've seen the same issues @mshockwave has seen.
https://github.com/llvm/llvm-project/pull/144402
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lenary wrote:
Do the fuchsia builders actually produce output on a failure? We seem to just
get exit code 1, but no indication of what filecheck had problems with.
https://github.com/llvm/llvm-project/pull/121829
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lenary wrote:
I'm going to land this, as I'm taking "I'm aligned with this fix" as approval
from garvit (I know he's in a different time zone, which may mean he's logged
off for the night)
https://github.com/llvm/llvm-project/pull/144582
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https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/144582
The openmp-offload-amdgpu-runtime-2 bot specifies default rtlib of compiler-rt,
but default unwindlib of libgcc. Change the tests to accept that there may be
`"--as-needed" "-lgcc_s" "--no-as-needed"` between `l
lenary wrote:
My plan is to modify the tests to accept that there might be unwindlib
arguments between `clang_rt.builtins.a` and `-lc`, which is where the breakage
is right now.
https://github.com/llvm/llvm-project/pull/121830
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lenary wrote:
The answer is yes, this builder does set a different unwindlib.
https://github.com/llvm/llvm-project/pull/121830
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lenary wrote:
@kewen12 I think I can see how to fix these tests, I'm just confused because
these tests seem to end up requesting both compiler-rt and libgcc. Is that bot
configured with a different default unwindlib to normal or something?
https://github.com/llvm/llvm-project/pull/121830
_
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/137854
>From f156620203b61fbe48c80b4b45c451f9a6c6eed9 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 29 Apr 2025 11:10:54 -0700
Subject: [PATCH 1/3] [RISCV] Xqccmp v0.3
---
clang/test/Driver/print-supported-ext
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/144398
None
>From b9e6e8f0570bad9b9d19179bd263dc3df40f8bdf Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Mon, 16 Jun 2025 10:18:10 -0700
Subject: [PATCH] [RISCV] Update Xqci to v0.13.0
---
clang/include/clang/Basi
lenary wrote:
> > Not related to this PR, but I'd like to raise the question here:
> > For configurable cores, what is the best way to specify the features?
> > `-mcpu` is meant to support the base configuration, but how can we specify
> > the additional optional extensions? Apparently, failing
lenary wrote:
I think this feature is really tough, the arm/aarch64 backends have got too
much complexity from similar features, mostly because their cpus have all their
optional features enabled by default.
I think if you can only enable additional extensions, that proposed syntax
would prob
https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/144022
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https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/142900
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lenary wrote:
I'm happy with this in that the test coverage looks adequate to me. I cannot
really verify that the list of extensions are correct, but they look reasonable
enough.
https://github.com/llvm/llvm-project/pull/142517
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lenary wrote:
Sorry, I must have hit "update branch" on the mobile interface by mistake.
https://github.com/llvm/llvm-project/pull/141172
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https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/141172
>From 036a3bd7024fe358d670b49d1d62bfe3cc0bc6d4 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Thu, 22 May 2025 15:05:30 +0800
Subject: [PATCH] [RISCV] Add pre-defined macro tests for Andes vendor
extension. NFC.
https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/141172
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https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/140979
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https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/137881
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https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/139519
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https://github.com/llvm/llvm-project/pull/137881
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https://github.com/llvm/llvm-project/pull/137881
>From 77e11986173c1687db5694544337026badb37448 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 29 Apr 2025 14:28:43 -0700
Subject: [PATCH 1/3] [RISCV] Xqci Extensions v0.10.0
This updates all the extension
https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/138498
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https://github.com/llvm/llvm-project/pull/137881
>From 77e11986173c1687db5694544337026badb37448 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 29 Apr 2025 14:28:43 -0700
Subject: [PATCH 1/2] [RISCV] Xqci Extensions v0.10.0
This updates all the extension
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/137881
This updates all the extensions to their version in the v0.10.0 spec.
All changes from this version are already implemented or are not relevant to
LLVM.
This change also alphabetises the lists of Xqci extension
https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/137865
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lenary wrote:
If the `"-target-feature" "+sscofpmf"` was already present in the test output,
just not looked for, then I think you should just mark this as `[NFC]`.
https://github.com/llvm/llvm-project/pull/137865
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https://github.com/llvm/llvm-project/pull/137854
>From f156620203b61fbe48c80b4b45c451f9a6c6eed9 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 29 Apr 2025 11:10:54 -0700
Subject: [PATCH 1/2] [RISCV] Xqccmp v0.3
---
clang/test/Driver/print-supported-ext
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/137854
All the changes for v0.2 and v0.3 are either already implemented, or irrelevant
to the compiler implementation.
>From f156620203b61fbe48c80b4b45c451f9a6c6eed9 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tu
lenary wrote:
I pushed an xfail as `31bd7a507152` and will look into the failures now.
https://github.com/llvm/llvm-project/pull/132481
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lenary wrote:
Sorry! I will look at it today. I'll push an xfail in the meantime, to get it
green again.
https://github.com/llvm/llvm-project/pull/132481
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https://github.com/lenary closed
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@@ -200,6 +203,149 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CFIInstBuilder(MBB, MI, MachineInstr::FrameDestroy).buildRestore(SCSPReg);
}
+// Insert instruction to swap mscratchsw with sp
+static void emitSiFiveCLICStackSwap(MachineFunction
lenary wrote:
I've resolved the merge conflict so I can merge this, now I'm back at work
after some travel. I'll let some pre-commit checks run before I finally hit
merge though.
https://github.com/llvm/llvm-project/pull/132481
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https://github.com/lenary approved this pull request.
LGTM when there are release notes.
https://github.com/llvm/llvm-project/pull/136694
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https://github.com/lenary commented:
Broadly happy, but I think two of the CSRs need to be 32-bit only, with tests.
https://github.com/llvm/llvm-project/pull/136556
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@@ -482,6 +482,14 @@ def : SysReg<"sctrdepth", 0x15f>;
def : SysReg<"vsctrctl", 0x24e>;
def : SysReg<"mctrctl", 0x34e>;
+//===---
+// Cycle and Instret privilege mode filtering (Smcntrpmf)
+//===--
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lenary wrote:
Oh, can you rename this. It's definitely not NFC, and should have "[RISCV]" in
the commit first line instead.
https://github.com/llvm/llvm-project/pull/135647
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https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/135647
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lenary wrote:
@kito-cheng sorted, we now hard error (without a crash trace) if you try to
combine frame pointers and preemptible interrupts
https://github.com/llvm/llvm-project/pull/132481
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https:
@@ -940,6 +947,14 @@ struct RISCVOperand final : public MCParsedAsmOperand {
[](int64_t Imm) { return Imm != INT64_MIN && isInt<5>(Imm - 1); });
}
+ bool isSImm18() const { return isBareSimmNLsbK<18, 0>(); }
+
+ bool isSImm18Lsb0() const { return isBareSimmNLsb0<18
@@ -535,21 +540,29 @@ RISCVMCCodeEmitter::getImmOpValueSlist(const MCInst &MI,
unsigned OpNo,
}
}
-uint64_t
-RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
+template
+unsigned
+RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
lenary wrote:
ping?
https://github.com/llvm/llvm-project/pull/132481
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Author: Sam Elliott
Date: 2025-03-24T13:04:00-07:00
New Revision: 4fb9650b21fc038ca044ac1ca7fcd5be0b44194a
URL:
https://github.com/llvm/llvm-project/commit/4fb9650b21fc038ca044ac1ca7fcd5be0b44194a
DIFF:
https://github.com/llvm/llvm-project/commit/4fb9650b21fc038ca044ac1ca7fcd5be0b44194a.diff
L
@@ -96,6 +96,21 @@ def simm32 : RISCVOp {
}];
}
+// A 32-bit signed immediate where the least significant bit is zero.
+def simm32_lsb0 : Operand {
+ let ParserMatchClass = SImmAsmOperand<32, "Lsb0">;
+ let PrintMethod = "printBranchOperand";
+ let EncoderMethod = "getImm
@@ -741,6 +750,28 @@ def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100,
"qc.c.mileaveret">;
} // Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1
+let Predicates = [HasVendorXqciio, IsRV32] in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
+ def QC_OU
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https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/132721
>From 12e1667575a3b506c5758bd976134e11ccb77f5c Mon Sep 17 00:00:00 2001
From: Harsh Chandel
Date: Mon, 24 Mar 2025 16:15:20 +0530
Subject: [PATCH 1/4] [RISCV] Add Qualcomm uC Xqciio (External Input Output)
exten
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/132721
>From 12e1667575a3b506c5758bd976134e11ccb77f5c Mon Sep 17 00:00:00 2001
From: Harsh Chandel
Date: Mon, 24 Mar 2025 16:15:20 +0530
Subject: [PATCH 1/3] [RISCV] Add Qualcomm uC Xqciio (External Input Output)
exten
@@ -486,6 +486,24 @@ def : SysReg<"mctrctl", 0x34e>;
// Vendor CSRs
//===---
+// XSfmclic
+let FeaturesRequired = [{ {RISCV::FeatureVendorXSfmclic} }] in {
+def : SysReg<"mtvt", 0x307>;
+def : SysReg<"mnxti", 0x345>;
+def : SysReg<"m
https://github.com/lenary commented:
I commented about the predicates (before i saw the other comments). I thought
they'd be ok to do in a follow-up, but you should just to the refactoring now
as it won't quite be NFC as I expected.
https://github.com/llvm/llvm-project/pull/132259
https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/132721
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lenary wrote:
Do you hit the same problem with `llvm::Bitset` as you do with `std::bitset`.
https://github.com/llvm/llvm-project/pull/132895
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https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/132520
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@@ -230,10 +230,16 @@ bool PEI::runOnMachineFunction(MachineFunction &MF) {
// with stack arguments.
TFI->spillFPBP(MF);
+ LLVM_DEBUG(llvm::dbgs() << "Before calculateCallFrameInfo \n");
lenary wrote:
Oh yeah, oops, lots of it. will remove.
https://gith
@@ -1502,6 +1659,9 @@ void
RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
auto *RVFI = MF.getInfo();
if (RVFI->isPushable(MF) && SavedRegs.test(RISCV::X26))
SavedRegs.set(RISCV::X27);
+
+ // SiFive Preemptible Interrupt Handlers need additional frame en
@@ -1502,6 +1659,9 @@ void
RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
auto *RVFI = MF.getInfo();
if (RVFI->isPushable(MF) && SavedRegs.test(RISCV::X26))
SavedRegs.set(RISCV::X27);
+
+ // SiFive Preemptible Interrupt Handlers need additional frame en
lenary wrote:
For Info, the last time this was proposed was in 2020:
https://reviews.llvm.org/D79521 - at that time, no vendor extensions had been
accepted upstream, and there was not yet a policy for upstream supporting
vendor extensions.
https://github.com/llvm/llvm-project/pull/132481
lenary wrote:
> Is there a reason why these aren't lowercase like the rest?
They match the existing names documented in
https://starfivetech.com/uploads/sifive-interrupt-cookbook-v1p2.pdf - we could
check them in clang case-insensitively, though.
https://github.com/llvm/llvm-project/pull/1324
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/132481
This Change adds support for two SiFive vendor attributes in clang:
- "SiFive-CLIC-preemptible"
- "SiFive-CLIC-stack-swap"
These can be given together, and can be combined with "machine", but
cannot be combined w
https://github.com/lenary approved this pull request.
LGTM. Thanks Harsh!
https://github.com/llvm/llvm-project/pull/132184
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@@ -378,6 +370,14 @@ def FeatureStdExtZca
"part of the C extension, excluding compressed "
"floating point loads/stores">;
+def FeatureStdExtC
+: RISCVExtension<2, 0, "Compressed Instructions", [FeatureStdExtZca]>,
+ RISCVExte
https://github.com/lenary approved this pull request.
LGTM, with one comment.
https://github.com/llvm/llvm-project/pull/132259
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@@ -856,6 +856,19 @@ void RISCVISAInfo::updateImplication() {
});
}
+ // Add Zcd if C and D are enabled.
+ if (Exts.count("c") && Exts.count("d") && !Exts.count("zcd")) {
+auto Version = findDefaultVersion("zcd");
+Exts["zcd"] = *Version;
+ }
+
+
@@ -378,6 +370,14 @@ def FeatureStdExtZca
"part of the C extension, excluding compressed "
"floating point loads/stores">;
+def FeatureStdExtC
+: RISCVExtension<2, 0, "Compressed Instructions", [FeatureStdExtZca]>,
+ RISCVExte
https://github.com/lenary edited
https://github.com/llvm/llvm-project/pull/132259
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@@ -25,8 +25,8 @@ addi a0, a1, 0
# CHECK: # encoding: [0xe0,0x1f]
addi s0, sp, 1020
-# CHECK: .option arch, -c
-.option arch, -c
+# CHECK: .option arch, -c, -zca
+.option arch, -c, -zca
lenary wrote:
This is because your predicates need a little bit of work,
lenary wrote:
There are lots of bugs like this in this area, this is not the only feature
like this. Should this be fixed in a more general way?
https://github.com/llvm/llvm-project/pull/132167
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h
https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/131094
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https://github.com/lenary approved this pull request.
LGTM but Craig may have more comments.
https://github.com/llvm/llvm-project/pull/131996
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@@ -96,6 +96,21 @@ def simm32 : RISCVOp {
}];
}
+// A 32-bit signed immediate where the least significant bit is zero.
+def simm32_lsb0 : Operand {
+ let ParserMatchClass = SImmAsmOperand<32, "Lsb0">;
+ let PrintMethod = "printBranchOperand";
+ let EncoderMethod = "getImm
https://github.com/lenary approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/131094
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@@ -401,6 +408,14 @@ def FeatureStdExtZcf
"Compressed Single-Precision Floating-Point Instructions",
[FeatureStdExtF, FeatureStdExtZca]>;
+def FeatureStdExtZclsd
+: RISCVExtension<1, 0,
+ "Compressed Load/Store
@@ -780,6 +780,14 @@ Error RISCVISAInfo::checkDependency() {
return getIncompatibleError("xwchc", "zcb");
}
+ if (Exts.count("zclsd") != 0) {
+if (XLen != 32)
+ return getError("'zclsd' is only supported for 'rv32'");
+
+if (Exts.count("zcf") != 0)
+
https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/128833
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https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/128833
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https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/130219
The Xqci 0.7.0 spec just came out, with some updates to Xqciint, bringing it to
v0.4. The main update of any relevance is that `qc.c.mienter` and
`qc.c.mienter.nest` now update both the stack pointer and the fra
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