Author: Shengchen Kan
Date: 2020-02-24T13:45:27+08:00
New Revision: 6a3506a208b90e65c719b0942376f46902a08945
URL:
https://github.com/llvm/llvm-project/commit/6a3506a208b90e65c719b0942376f46902a08945
DIFF:
https://github.com/llvm/llvm-project/commit/6a3506a208b90e65c719b0942376f46902a08945.diff
Author: Shengchen Kan
Date: 2020-05-13T14:48:46+08:00
New Revision: ad60ff70eb56a7d198e613152f9974d5d4baabd4
URL:
https://github.com/llvm/llvm-project/commit/ad60ff70eb56a7d198e613152f9974d5d4baabd4
DIFF:
https://github.com/llvm/llvm-project/commit/ad60ff70eb56a7d198e613152f9974d5d4baabd4.diff
Author: Shengchen Kan
Date: 2020-05-28T13:17:14+08:00
New Revision: 49544499954912c5a0f02014de53e0bc0234c7af
URL:
https://github.com/llvm/llvm-project/commit/49544499954912c5a0f02014de53e0bc0234c7af
DIFF:
https://github.com/llvm/llvm-project/commit/49544499954912c5a0f02014de53e0bc0234c7af.diff
Author: Shengchen Kan
Date: 2020-04-09T19:34:12+08:00
New Revision: 792b10978dfdd424721fbf0ffd99c35d628f2321
URL:
https://github.com/llvm/llvm-project/commit/792b10978dfdd424721fbf0ffd99c35d628f2321
DIFF:
https://github.com/llvm/llvm-project/commit/792b10978dfdd424721fbf0ffd99c35d628f2321.diff
Author: Shengchen Kan
Date: 2020-03-12T09:26:51+08:00
New Revision: 560aa53f8fe58abcbc4bb441b631e8a401ee78fe
URL:
https://github.com/llvm/llvm-project/commit/560aa53f8fe58abcbc4bb441b631e8a401ee78fe
DIFF:
https://github.com/llvm/llvm-project/commit/560aa53f8fe58abcbc4bb441b631e8a401ee78fe.diff
Author: Shengchen Kan
Date: 2020-03-12T10:03:41+08:00
New Revision: ab69cd0779c529519eb7d26e0fa1b8dfb505f838
URL:
https://github.com/llvm/llvm-project/commit/ab69cd0779c529519eb7d26e0fa1b8dfb505f838
DIFF:
https://github.com/llvm/llvm-project/commit/ab69cd0779c529519eb7d26e0fa1b8dfb505f838.diff
Author: Shengchen Kan
Date: 2020-03-12T10:56:39+08:00
New Revision: 214d24e1f8e0737a5aa2e2c52a1ae095fb1c1abd
URL:
https://github.com/llvm/llvm-project/commit/214d24e1f8e0737a5aa2e2c52a1ae095fb1c1abd
DIFF:
https://github.com/llvm/llvm-project/commit/214d24e1f8e0737a5aa2e2c52a1ae095fb1c1abd.diff
Author: Shengchen Kan
Date: 2020-06-03T14:59:14+08:00
New Revision: ac47588bc4ff5927a01ed6fcd269ce86aba52a7c
URL:
https://github.com/llvm/llvm-project/commit/ac47588bc4ff5927a01ed6fcd269ce86aba52a7c
DIFF:
https://github.com/llvm/llvm-project/commit/ac47588bc4ff5927a01ed6fcd269ce86aba52a7c.diff
Author: Shengchen Kan
Date: 2020-06-08T23:14:16+08:00
New Revision: 2c63ea6eded3eed4018306363c28b7f63d7b5898
URL:
https://github.com/llvm/llvm-project/commit/2c63ea6eded3eed4018306363c28b7f63d7b5898
DIFF:
https://github.com/llvm/llvm-project/commit/2c63ea6eded3eed4018306363c28b7f63d7b5898.diff
@@ -954,6 +954,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__CCMP__");
if (HasCF)
Builder.defineMacro("__CF__");
+ if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD)
KanRobert wrote:
Add comment
`Condition
https://github.com/KanRobert approved this pull request.
LGTM with a suggestion
https://github.com/llvm/llvm-project/pull/88343
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https://github.com/KanRobert approved this pull request.
LGTM. My understanding is that this flag is used for reducing compile time and
debug only.
https://github.com/llvm/llvm-project/pull/90013
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@@ -462,12 +462,12 @@ TARGET_BUILTIN(__builtin_ia32_blendvps256,
"V8fV8fV8fV8f", "ncV:256:", "avx")
TARGET_BUILTIN(__builtin_ia32_shufpd256, "V4dV4dV4dIi", "ncV:256:", "avx")
TARGET_BUILTIN(__builtin_ia32_shufps256, "V8fV8fV8fIi", "ncV:256:", "avx")
TARGET_BUILTIN(__builtin_ia
KanRobert wrote:
My understanding is that you change the required feature of
__builtin_ia32_cmp[p|s][s|d] from avx to sse for some condition codes. The
title is not accurate.
https://github.com/llvm/llvm-project/pull/84136
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@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because t
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because t
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because t
KanRobert wrote:
Still not understand. Shouldn't the target feature of the caller be passed to
the intrinsic when checking the argument of the intrinsic?
https://github.com/llvm/llvm-project/pull/84136
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KanRobert wrote:
> > Still not understand. Shouldn't the target feature of the caller be passed
> > to the intrinsic when checking the argument of the intrinsic?
>
> The target features passing from option can be passed to Semachecking. It's
> special for attribute_target, which is handled in
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/84136
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@@ -1763,10 +1823,14 @@ void
X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl &Values) con
}
ArrayRef X86TargetInfo::getGCCRegNames() const {
+ if (HasEGPR)
+return llvm::ArrayRef(ExtendedGCCRegNames);
return llvm::ArrayRef(GCCRegNames);
KanRobert
@@ -1763,10 +1823,14 @@ void
X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl &Values) con
}
ArrayRef X86TargetInfo::getGCCRegNames() const {
+ if (HasEGPR)
+return llvm::ArrayRef(ExtendedGCCRegNames);
return llvm::ArrayRef(GCCRegNames);
KanRobert
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
KanRobert wrote:
I
@@ -83,8 +85,23 @@ const TargetInfo::AddlRegName AddlRegNames[] = {
{{"r13d", "r13w", "r13b"}, 43},
{{"r14d", "r14w", "r14b"}, 44},
{{"r15d", "r15w", "r15b"}, 45},
+{{"r16d", "r16w", "r16b"}, 165},
KanRobert wrote:
Where does the 165 come from?
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
KanRobert wrote:
We
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
KanRobert wrote:
Cr
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o /dev/null
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-feature +egpr %s -o
/dev/null
+
+int foo(void) {
+ register int a __asm__("ebx");
+#ifdef __EGPR__
KanRobert wrote:
ba
KanRobert wrote:
Rename it to inline-asm-gcc-regs.c?
https://github.com/llvm/llvm-project/pull/91323
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/91323
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Author: Shengchen Kan
Date: 2024-05-11T15:55:59+08:00
New Revision: 575177f610274e909a17450c29d2e997f7a7f13d
URL:
https://github.com/llvm/llvm-project/commit/575177f610274e909a17450c29d2e997f7a7f13d
DIFF:
https://github.com/llvm/llvm-project/commit/575177f610274e909a17450c29d2e997f7a7f13d.diff
KanRobert wrote:
Please put the corresponding GCC links for your description
https://github.com/llvm/llvm-project/pull/92338
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@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
This should not
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
```
std::stri
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
Will the featur
https://github.com/KanRobert edited
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@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> `mcmodel` may
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> > Will the fe
@@ -450,6 +450,8 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullBFloat16 = true;
} else if (Feature == "+egpr") {
HasEGPR = true;
+} else if (Feature == "+inline-asm-use-gpr32") {
KanRobert wrote:
> SSELevel reli
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/92338
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KanRobert wrote:
Merge the two tests into one and put it under apx directory.
https://github.com/llvm/llvm-project/pull/92338
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@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
--
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -346,6 +346,9 @@ def FeatureNF : SubtargetFeature<"nf", "HasNF", "true",
"Support status flags update suppression">;
def FeatureCF : SubtargetFeature<"cf", "HasCF", "true",
"Support conditional faulting">;
+de
https://github.com/KanRobert deleted
https://github.com/llvm/llvm-project/pull/92338
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@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+
@@ -58255,6 +58281,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
}
break;
}
+ } else if (Constraint.size() == 2 && Constraint[0] == 'j') {
+switch (Constraint[1]) {
+default:
+ break;
+case 'R':
+ if
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 < %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: not llc -mtriple=x86_64 -mattr=+egpr < %s 2>&1 | FileCheck %s
--check-prefix=ERR
+; RUN: llc -mtripl
@@ -5418,6 +5418,8 @@ X86:
operand will get allocated only to RAX -- if two 32-bit operands are needed,
you're better off splitting it yourself, before passing it to the asm
statement.
+- ``jR``: An 8, 16, 32, or 64-bit integer EGPR when EGPR feature is on.
+ Otherwise,
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc -mtriple=x86_64 %s 2>&1 | FileCheck %s --check-prefix=ERR
+; RUN: llc -mtriple=x86_64 -mattr=+egpr < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 -mattr=+egpr,+inline-a
@@ -58024,15 +58043,22 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
-return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
+
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/75571
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KanRobert wrote:
One more justification...
https://www.felixcloutier.com/x86/vscatterpf0dps:vscatterpf0qps:vscatterpf0dpd:vscatterpf0qpd
The assembler support for some KNL instructions is buggy
https://github.com/llvm/llvm-project/blob/31429e7a89590f88034920edd3e997aeabff8124/llvm/test/MC/X86/a
https://github.com/KanRobert approved this pull request.
LGTM, but please put the link for the discussion in GCC community in description
https://github.com/llvm/llvm-project/pull/103898
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https://l
https://github.com/KanRobert created
https://github.com/llvm/llvm-project/pull/106681
For
movname@GOTPCREL(%rip), %reg
test %reg, name@GOTPCREL(%rip)
binop name@GOTPCREL(%rip), %reg
where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructi
https://github.com/KanRobert converted_to_draft
https://github.com/llvm/llvm-project/pull/106681
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https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/2] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/3] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/4] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/106681
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KanRobert wrote:
TODO:
* [ ] Pass tests lld/test/ELF/x86-64-gotpc-relax.s and
lld/test/ELF/x86-64-gotpc-relax-nopic.s
https://github.com/llvm/llvm-project/pull/106681
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https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/5] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert ready_for_review
https://github.com/llvm/llvm-project/pull/106681
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https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/6] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/106681
>From 8d8aea0d9d6b85a3b279a1c60b50cf9b859d6919 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 25 Jun 2024 20:33:10 +0800
Subject: [PATCH 1/7] [X86,lld] Add relocation R_X86_64_REX2_GOTPCRELX
For
https://github.com/KanRobert approved this pull request.
MC and foldtable change LGTM
https://github.com/llvm/llvm-project/pull/101600
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/104781
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KanRobert wrote:
> I suppose the name of relocation used by binutils is
> R_X86_64_CODE_4_GOTPCRELX Also binutils has added
> R_X86_64_CODE_5_GOTPCRELX/R_X86_64_CODE_6_GOTPCRELX, for evex relocation
> Refer to
> [bminor/binutils-gdb@3d5a60d](https://github.com/bminor/binutils-gdb/commit/3d5a6
https://github.com/KanRobert created
https://github.com/llvm/llvm-project/pull/78901
None
>From 6e490075f52d8b8cefcdde59fe24914b80a64039 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sun, 21 Jan 2024 22:02:21 +0800
Subject: [PATCH] [X86][Driver] Enable feature ndd for -mapxf
---
clang/i
@@ -803,10 +803,10 @@
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd
-x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64
-mapx-features=ccmp -x c -E -dM -o - %s | FileCheck --check-pr
@@ -803,10 +803,10 @@
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd
-x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64
-mapx-features=ccmp -x c -E -dM -o - %s | FileCheck --check-pr
@@ -803,10 +803,10 @@
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd
-x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s
// RUN: %clang -target x86_64-unknown-unknown -march=x86-64
-mapx-features=ccmp -x c -E -dM -o - %s | FileCheck --check-pr
https://github.com/KanRobert edited
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KanRobert wrote:
Thanks! @phoebewang
https://github.com/llvm/llvm-project/pull/78901
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https://github.com/KanRobert closed
https://github.com/llvm/llvm-project/pull/78901
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https://github.com/KanRobert commented:
Update the tests for `m512_maskz_cvt_roundepu64_ps` e.t.c (in
avx512dq-builtins.c )?
https://github.com/llvm/llvm-project/pull/99691
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@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
@@ -8367,6 +8369,9 @@ void ClangAs::AddX86TargetArgs(const ArgList &Args,
addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs,
/*IsLTO=*/false);
+ if (Args.hasArg(options::OPT_msse2avx))
+Args.AddLastArg(CmdArgs, options::OPT_msse2avx
@@ -140,6 +141,10 @@
llvm::mc::RegisterMCTargetOptionsFlags::RegisterMCTargetOptionsFlags() {
cl::init(true));
MCBINDOPT(X86RelaxRelocations);
+ static cl::opt X86Sse2Avx(
+ "x86-sse2avx", cl::desc("Convert SSE Instructions to AVX Instructions"));
--
@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_
https://github.com/KanRobert deleted
https://github.com/llvm/llvm-project/pull/96860
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https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/96860
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https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/96860
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https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/96860
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https://github.com/KanRobert edited
https://github.com/llvm/llvm-project/pull/96860
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@@ -2711,6 +2711,8 @@ static void CollectArgsForIntegratedAssembler(Compilation
&C,
}
if (!UseRelaxRelocations)
CmdArgs.push_back("-mrelax-relocations=no");
+ if (Args.hasArg(options::OPT_msse2avx))
+CmdArgs.push_back("-msse2avx");
KanRobert wrote
https://github.com/KanRobert closed
https://github.com/llvm/llvm-project/pull/96860
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Author: Shengchen Kan
Date: 2024-07-16T10:59:12+08:00
New Revision: d82c75ebc0483971b768dd5ff077789262ffd9c0
URL:
https://github.com/llvm/llvm-project/commit/d82c75ebc0483971b768dd5ff077789262ffd9c0
DIFF:
https://github.com/llvm/llvm-project/commit/d82c75ebc0483971b768dd5ff077789262ffd9c0.diff
@@ -175,8 +175,6 @@ X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16",
34)
X86_FEATURE_COMPAT(AVX512VP2INTERSECT, "avx512vp2intersect", 35)
// Below Features has some missings comparing to gcc, it's because gcc has some
// not one-to-one mapped in llvm.
-X86_FEATURE_
Author: Shengchen Kan
Date: 2024-07-19T12:34:41+08:00
New Revision: 88e9bd822fe088eff74f49081b890071538fa40c
URL:
https://github.com/llvm/llvm-project/commit/88e9bd822fe088eff74f49081b890071538fa40c
DIFF:
https://github.com/llvm/llvm-project/commit/88e9bd822fe088eff74f49081b890071538fa40c.diff
@@ -309,8 +309,8 @@
// HRESET: "-target-feature" "+hreset"
// NO-HRESET: "-target-feature" "-hreset"
-// RUN: %clang --target=i386 -march=i386 -muintr %s -### 2>&1 | FileCheck
-check-prefix=UINTR %s
-// RUN: %clang --target=i386 -march=i386 -mno-uintr %s -### 2>&1 | FileCheck
@@ -248,6 +248,10 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name));
}
+ llvm::StringSet<> SubFeaturesOfAPX = {"egpr", "push2pop2", "ppx", "ndd",
+
@@ -266,13 +270,24 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
}
bool IsNegative = Name.starts_with("no-");
+
+bool Not64Bit = ArchType != llvm::Triple::x86_64;
KanRobert wrote:
It would not. We check the option
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/101151
>From 650f29dd40714ebe52bf5d0a407bd45b9d248269 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 30 Jul 2024 16:26:39 +0800
Subject: [PATCH 1/4] [Driver,CodeGen] Report error when enabling 64-bit-only
f
@@ -309,8 +309,8 @@
// HRESET: "-target-feature" "+hreset"
// NO-HRESET: "-target-feature" "-hreset"
-// RUN: %clang --target=i386 -march=i386 -muintr %s -### 2>&1 | FileCheck
-check-prefix=UINTR %s
-// RUN: %clang --target=i386 -march=i386 -mno-uintr %s -### 2>&1 | FileCheck
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/101151
>From 650f29dd40714ebe52bf5d0a407bd45b9d248269 Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Tue, 30 Jul 2024 16:26:39 +0800
Subject: [PATCH 1/5] [Driver,CodeGen] Report error when enabling 64-bit-only
f
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