@@ -0,0 +1,51 @@
+
+// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=60 -DOMP60 %s
-Wuninitialized
+
+// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=60 -DOMP60 %s
-Wuninitialized
+
+// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=52 -DOMP52 %s
-Wuninitialize
shiltian wrote:
Looking at this now, it doesn't seem the same as it was at the start. For the
latest changes, I think @arsenm made it clear that waves-per-eu values should
always give way to the values calculated from flat-workgroup-size if they
differ, since flat-workgroup-size is ABI and wav
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/155478
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The title needs to be more specific.
https://github.com/llvm/llvm-project/pull/155138
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https://github.com/shiltian commented:
Has `dyn_groupprivate` already been approved to be in 6.1 or is this just a PoC
implementation?
https://github.com/llvm/llvm-project/pull/152651
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https://github.com/llvm/llvm-project/pull/153680
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@@ -159,6 +159,119 @@ Value *EmitAMDGPUGridSize(CodeGenFunction &CGF, unsigned
Index) {
llvm::MDNode::get(CGF.getLLVMContext(), {}));
return LD;
}
+// Lowers __builtin_amdgcn_ds_bpermute to the corresponding LLVM intrinsic with
+// careful bit-level coercio
@@ -159,6 +159,119 @@ Value *EmitAMDGPUGridSize(CodeGenFunction &CGF, unsigned
Index) {
llvm::MDNode::get(CGF.getLLVMContext(), {}));
return LD;
}
+// Lowers __builtin_amdgcn_ds_bpermute to the corresponding LLVM intrinsic with
+// careful bit-level coercio
@@ -18,6 +18,132 @@
#include "llvm/Support/AtomicOrdering.h"
#include
+namespace {
+
+using llvm::StringRef;
+using namespace clang;
+
+/// Attempts to apply a user-defined conversion on Arg at ArgIndex to a
+/// 32-bit-compatible type. If successful, updates TheCall's argume
https://github.com/shiltian deleted
https://github.com/llvm/llvm-project/pull/153501
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@@ -159,6 +159,119 @@ Value *EmitAMDGPUGridSize(CodeGenFunction &CGF, unsigned
Index) {
llvm::MDNode::get(CGF.getLLVMContext(), {}));
return LD;
}
+// Lowers __builtin_amdgcn_ds_bpermute to the corresponding LLVM intrinsic with
+// careful bit-level coercio
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/151964
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https://github.com/llvm/llvm-project/pull/135079
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/151058
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shiltian wrote:
FWIW, https://github.com/llvm/llvm-project/pull/143058 seems like doing the
same thing.
https://github.com/llvm/llvm-project/pull/138294
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https://github.com/shiltian approved this pull request.
Is clang tools always installed?
https://github.com/llvm/llvm-project/pull/150965
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https://github.com/shiltian commented:
it doesn't seem to be tested?
https://github.com/llvm/llvm-project/pull/150580
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/150493
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/148627
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shiltian wrote:
I don't know which one. My PRs yesterday afternoon have a lot of crash in ADT
but after rebase a couple of hours later they were gone. I suppose that would
be the one.
https://github.com/llvm/llvm-project/pull/125556
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shiltian wrote:
Someone else messed up it. The commit has been reverted.
https://github.com/llvm/llvm-project/pull/125556
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/149684
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https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149528
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https://github.com/llvm/llvm-project/pull/149528
>From 3fb65bcda47f66a47c8295e04102a3a1d675dbd7 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:36:56 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sat_pk4_i4_[i8,u8]` on gfx1250
Co-au
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/149528
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https://github.com/llvm/llvm-project/pull/149518
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From d58f9605434bfc4de1820f7c6beabd82586a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From f7c11e672cebd2488582ee89e66d9777182db1e1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From e6d5fd17af108d454e43a6489eb7580bf007a170 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 8f89191a1714b2e891eda67d844d32be2ccfc27a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 1d045407b88bc8efae91410223e8ba980cdec6d1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 4d850d602b45130ae958776cd353512116bd5862 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
shiltian wrote:
### Merge activity
* **Jul 18, 4:46 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149518).
https://github.com/llvm/llvm-project/pull/149518
___
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 33991acfd14b041071d112de032afe94c6bedf35 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/149518
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https://github.com/llvm/llvm-project/pull/149450
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149518
>From 345d4d9de11d21c1b087cdf88de22f0d90a7ba9f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 10:02:30 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_permlane16_swap_b32` on gfx1250
Co-a
shiltian wrote:
### Merge activity
* **Jul 18, 2:58 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149450).
https://github.com/llvm/llvm-project/pull/149450
___
@@ -4007,7 +4007,8 @@ SDValue
AMDGPUTargetLowering::performIntrinsicWOChainCombine(
case Intrinsic::amdgcn_rcp_legacy:
case Intrinsic::amdgcn_rsq_legacy:
case Intrinsic::amdgcn_rsq_clamp:
- case Intrinsic::amdgcn_tanh: {
+ case Intrinsic::amdgcn_tanh:
+ case Intrinsic
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149450
>From e35cd5506ed733fcb62eab4c28ab4e9f5966216f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 00:26:15 -0400
Subject: [PATCH 1/2] [AMDGPU] Add support for `v_prng_b32` on gfx1250
Co-authored
@@ -4007,7 +4007,8 @@ SDValue
AMDGPUTargetLowering::performIntrinsicWOChainCombine(
case Intrinsic::amdgcn_rcp_legacy:
case Intrinsic::amdgcn_rsq_legacy:
case Intrinsic::amdgcn_rsq_clamp:
- case Intrinsic::amdgcn_tanh: {
+ case Intrinsic::amdgcn_tanh:
+ case Intrinsic
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/149450
>From e35cd5506ed733fcb62eab4c28ab4e9f5966216f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 18 Jul 2025 00:26:15 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_prng_b32` on gfx1250
Co-authored-by:
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/149450
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shiltian wrote:
### Merge activity
* **Jul 18, 12:42 PM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149447).
https://github.com/llvm/llvm-project/pull/149447
__
https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149360
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https://github.com/llvm/llvm-project/pull/149360
>From 10b9379f759506e4e1e3c1cab1191ed386609ebe Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 13:03:14 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_f32` on gfx1250
Co-authored-by:
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/149360
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shiltian wrote:
### Merge activity
* **Jul 17, 6:41 PM UTC**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149355).
https://github.com/llvm/llvm-project/pull/149355
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shiltian wrote:
Oh nice catch. Thanks.
https://github.com/llvm/llvm-project/pull/149355
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shiltian wrote:
but we do have `v_cos_bf16` in `llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s`?
https://github.com/llvm/llvm-project/pull/149355
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https://github.com/llvm/llvm-project/pull/149355
>From 29b54575b3e64372750466dfafab971697f402f1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 12:45:33 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sin_bf16_e64` on gfx1250
Co-authored
shiltian wrote:
* **#149355** https://app.graphite.dev/github/pr/llvm/llvm-project/149355?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/149
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149355
Co-authored-by: Mekhanoshin, Stanislav
>From a6b7ccf491c4d88b18bfdba0dbf839030df189ec Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 17 Jul 2025 12:45:33 -0400
Subject: [PATCH] [AMDGPU] Add support for
@@ -610,7 +610,7 @@ void StmtPrinter::VisitObjCAtTryStmt(ObjCAtTryStmt *Node) {
}
}
- if (auto *FS = static_cast(Node->getFinallyStmt())) {
+ if (auto *FS = Node->getFinallyStmt()) {
shiltian wrote:
If there is no cast, then we'd want to use the type
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/149338
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/149340
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/149339
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https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/149241
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https://github.com/llvm/llvm-project/pull/149241
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https://github.com/llvm/llvm-project/pull/149241
>From 8012a2d62f910c81a38c1c8d1de1a5bbd797d22f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 16 Jul 2025 23:48:48 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_sin_bf16` on gfx1250
Co-authored-by:
https://github.com/shiltian closed
https://github.com/llvm/llvm-project/pull/149229
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shiltian wrote:
### Merge activity
* **Jul 17, 12:41 PM UTC**: A user started a stack merge that includes this
pull request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/149229).
https://github.com/llvm/llvm-project/pull/149229
__
@@ -252,6 +252,15 @@ TARGET_BUILTIN(__builtin_amdgcn_flat_atomic_fmax_f64,
"dd*0d", "t", "gfx90a-inst
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_f64, "dd*3d", "t",
"gfx90a-insts")
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_f32, "ff*3f", "t", "gfx8-insts")
+TARGET_BUI
@@ -25,4 +25,27 @@ define amdgpu_ps void @llvm_log2_bf16_s(ptr addrspace(1)
%out, bfloat inreg %src
ret void
}
+define amdgpu_ps void @llvm_exp2_bf16_v(ptr addrspace(1) %out, bfloat %src) {
+; GCN-LABEL: llvm_exp2_bf16_v:
+; GCN: ; %bb.0:
+; GCN-NEXT:v_exp_bf16_e3
shiltian wrote:
* **#149194** https://app.graphite.dev/github/pr/llvm/llvm-project/149194?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/149
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/149194
Co-authored-by: Mekhanoshin, Stanislav
>From 296077854b4bcad36f9b924da1dbfe4376d8b4d5 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 16 Jul 2025 17:31:42 -0400
Subject: [PATCH] [AMDGPU] Add support for
shiltian wrote:
* **#148916** https://app.graphite.dev/github/pr/llvm/llvm-project/148916?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/148
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/148916
Co-authored-by: Mekhanoshin, Stanislav
>From b0c51e4f67e0740d916d1596ced8f93228d93b1c Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 15 Jul 2025 14:10:18 -0400
Subject: [PATCH] [AMDGPU] Add support for
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/148871
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shiltian wrote:
FWIW, the crash still exists.
https://github.com/llvm/llvm-project/pull/147425
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/147425
>From f75f85e997f95bd29e244e199d16c89dffca1232 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 14 Jul 2025 12:56:54 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_bf16` on gfx1250
Co-authored-by
@@ -2,169 +2,69 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble
-show-encoding < %s | FileChec
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/147425
>From 2c36f0664993d54841245fe62d062af3b7332c97 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 14 Jul 2025 12:56:54 -0400
Subject: [PATCH] [AMDGPU] Add support for `v_tanh_bf16` on gfx1250
Co-authored-by
@@ -704,12 +704,12 @@ void diagnoseUnknownMMRAASName(const MachineInstr &MI,
StringRef AS) {
DiagnosticInfoUnsupported(Fn, Str.str(), MI.getDebugLoc(), DS_Warning));
}
-/// Reads \p MI's MMRAs to parse the "amdgpu-as" MMRA.
+/// Reads \p MI's MMRAs to parse the "amdgpu-
shiltian wrote:
This PR is messed up at this moment.
https://github.com/llvm/llvm-project/pull/147425
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@@ -266,7 +266,7 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple
&Triple,
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
CUMode = !(GPUFeatures & llvm::AMDGPU::FEATURE_WGP);
- for (auto F : {"image-insts", "gws", "vmem-to-lds-load-insts"})
+ for (auto F : {
https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/147558
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@@ -2,51 +2,41 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble
-show-encoding < %s | FileCheck
@@ -2,51 +2,41 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble
-show-encoding < %s | FileCheck
shiltian wrote:
For some reason there is a crash in
`llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll`.
```
LLVM ERROR: Cannot select: t28: ch = store<(store (s16) into %ir.out.load,
addrspace 1)> t0, t27, t30, undef:i64
t27: i16 = bitcast t21
t21: bf16 = llvm.amdgcn.tanh TargetConstant:i64<
@@ -13658,6 +13658,7 @@ bool SITargetLowering::isCanonicalized(Register Reg,
const MachineFunction &MF,
case Intrinsic::amdgcn_frexp_mant:
case Intrinsic::amdgcn_fdot2:
case Intrinsic::amdgcn_trig_preop:
+case Intrinsic::amdgcn_tanh:
shiltian w
@@ -13658,6 +13658,7 @@ bool SITargetLowering::isCanonicalized(Register Reg,
const MachineFunction &MF,
case Intrinsic::amdgcn_frexp_mant:
case Intrinsic::amdgcn_fdot2:
case Intrinsic::amdgcn_trig_preop:
+case Intrinsic::amdgcn_tanh:
shiltian w
@@ -1432,6 +1442,26 @@ static bool runImpl(Module &M, AnalysisGetter &AG,
TargetMachine &TM,
} else if (auto *CmpX = dyn_cast(&I)) {
A.getOrCreateAAFor(
IRPosition::value(*CmpX->getPointerOperand()));
+ } else if (auto *II = dyn_cast(&I)) {
+
@@ -5501,7 +5505,32 @@ struct AAAlignCallSiteReturned final
using Base = AACalleeToCallSite;
AAAlignCallSiteReturned(const IRPosition &IRP, Attributor &A)
: Base(IRP, A) {}
+ ChangeStatus updateImpl(Attributor &A) override {
+SmallVector Values;
+SmallVector
@@ -85,7 +85,7 @@ __amdgpu_buffer_rsrc_t
test_amdgcn_make_buffer_p0_nullptr(short stride, int num,
// CHECK-LABEL: @test_amdgcn_make_buffer_p1_nullptr(
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call ptr addrspace(8)
@llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr
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https://github.com/llvm/llvm-project/pull/146944
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146987
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146636
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146707
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https://github.com/shiltian approved this pull request.
https://github.com/llvm/llvm-project/pull/146706
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shiltian wrote:
I see. That makes sense. Worth a release note item.
https://github.com/llvm/llvm-project/pull/146594
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https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/146594
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@@ -83,6 +83,84 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
case AMDGPU::BI__builtin_amdgcn_update_dpp: {
return checkMovDPPFunctionCall(TheCall, 6, 2);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin
@@ -83,6 +83,84 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
case AMDGPU::BI__builtin_amdgcn_update_dpp: {
return checkMovDPPFunctionCall(TheCall, 6, 2);
}
+ case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32:
+ case AMDGPU::BI__builtin
@@ -635,5 +635,66 @@ TARGET_BUILTIN(__builtin_amdgcn_bitop3_b16, "IUi",
"nc", "bitop3-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf16_f32, "V2yV2yfUiIb", "nc",
"f32-to-f16bf16-cvt-sr-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc",
"f32-to-
shiltian wrote:
Why not stick with `--offload-arch` for generic use? I'm not really sure about
the motivation.
https://github.com/llvm/llvm-project/pull/146594
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