[PATCH] D94403: [RISCV] Implement new architecture extension macros

This revision was automatically updated to reflect the committed changes. Closed by commit rG666815d61bc2: [RISCV] Implement new architecture extension macros (authored by simoncook). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94403/new/ https://

[PATCH] D94403: [RISCV] Implement new architecture extension macros

simoncook updated this revision to Diff 318869. simoncook added a comment. - Update to bitmanip 0.93 - Expand and support vector as per workaround in D95146 - Add negative testing (check __riscv_b not defined for just subextension) Repository: rG LLVM Github

[PATCH] D94930: [RISCV] Add support for Zvamo/Zvlsseg to driver

This revision was automatically updated to reflect the committed changes. Closed by commit rGafd483e57d16: [RISCV] Add support for Zvamo/Zvlsseg to driver (authored by simoncook). Changed prior to commit: https://reviews.llvm.org/D94930?vs=317408&id=318868#toc Repository: rG LLVM Github Mono

[PATCH] D94403: [RISCV] Implement new architecture extension macros

simoncook updated this revision to Diff 317591. simoncook added a comment. Have 'b'/'v' features imply subfeatures Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94403/new/ https://reviews.llvm.org/D94403 Files: clang/lib/Basic/Targets/RISCV.cpp

[PATCH] D94403: [RISCV] Implement new architecture extension macros

simoncook updated this revision to Diff 317409. simoncook added a comment. Rebase on D94930 to show updated version Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94403/new/ https://reviews.llvm.org/D94403 Files:

[PATCH] D94930: [RISCV] Add support for Zvamo/Zvlsseg to driver

simoncook created this revision. simoncook added reviewers: asb, luismarques, kito-cheng. Herald added subscribers: frasercrmck, NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc2

[PATCH] D94403: [RISCV] Implement new architecture extension macros

simoncook added a comment. In D94403#2504046 , @kito-cheng wrote: > Thanks you implement that on clang, I think it's really great to included > that in LLVM 12 release. > > I would like to define marco for sub-extension too, I know that's my fault, I > d

[PATCH] D94403: [RISCV] Implement new architecture extension macros

simoncook updated this revision to Diff 315805. simoncook added a comment. Correct constant used in macros, 2.0 should be 200 not 2000 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D94403/new/ https://reviews.llvm.org/D94403 Files: clang/

[PATCH] D94403: [RISCV] Implement new architecture extension macros

simoncook created this revision. simoncook added reviewers: asb, luismarques, kito-cheng. Herald added subscribers: frasercrmck, NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzhen

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

simoncook added a comment. In D80802#2156221 , @HsiangKai wrote: > The modification is put in D81213 . Ah ok, missed that, thanks for pointing it out Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION ht

[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

simoncook added a comment. Since this patch replaces 0.8 support with 0.9, it should include an update to the version check in `clang/lib/Driver/ToolChains/Arch/RISCV.cpp` to match. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80802/new/ https://

[PATCH] D83819: [RISCV] Add error checking for extensions missing separating underscores

This revision was automatically updated to reflect the committed changes. Closed by commit rGde7bf722c23a: [RISCV] Add error checking for extensions missing separating underscores (authored by simoncook). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/

[PATCH] D83819: [RISCV] Add error checking for extensions missing separating underscores

simoncook created this revision. simoncook added reviewers: asb, lenary, edward-jones, lewis-revill. Herald added subscribers: cfe-commits, evandro, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, zzhe

[PATCH] D81946: [WIP][RISCV] Enable multilib support even without a detected GCC install

simoncook added a comment. Thanks for this Ed. I've tried building a toolchain with it and noticed a couple of things: 1. Printing the set of multilibs doesn't provide a default, I think that should still be defined and printed with `-print-multi-libs` 2. There's a slight path finding issue if

[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

simoncook added a reviewer: simoncook. simoncook added a comment. This is looking good, overall the patch is nicely laid out which has made it easy to compare against the spec. I've made a few comments, mostly about ordering of instructions so that they are identical to the spec. One question,

[PATCH] D71553: [RISCV] Add Clang frontend support for Bitmanip extension

This revision was automatically updated to reflect the committed changes. Closed by commit rG61ff29637501: [RISCV] Add Clang frontend support for Bitmanip extension (authored by s.egerton, committed by simoncook). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

This revision was automatically updated to reflect the committed changes. Closed by commit rGdd1ee6dc076f: [RISCV] Support experimental/unratified extensions (authored by simoncook). Changed prior to commit: https://reviews.llvm.org/D73891?vs=250770&id=256369#toc Repository: rG LLVM Github M

[PATCH] D71553: [RISCV] Add Clang frontend support for Bitmanip extension

simoncook updated this revision to Diff 250871. simoncook added a comment. Address feedback Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71553/new/ https://reviews.llvm.org/D71553 Files: clang/lib/Basic/Targets/RISCV.cpp clang/lib/Basic/Targe

[PATCH] D71553: [RISCV] Add Clang frontend support for Bitmanip extension

simoncook updated this revision to Diff 250771. simoncook added a comment. Herald added a subscriber: evandro. Rebase on new dependencies Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71553/new/ https://reviews.llvm.org/D71553 Files: clang/lib/B

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

simoncook updated this revision to Diff 250770. simoncook added a comment. - Update to match latest dependencies - Handle adding "experimental-" to SubtargetFeatures for experimental features Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D73891/new/

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

simoncook updated this revision to Diff 243502. simoncook added a comment. Rebase, incorporate changes suggested by Lewis Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D73891/new/ https://reviews.llvm.org/D73891 Files: clang/include/clang/Driver/

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

simoncook updated this revision to Diff 243325. simoncook added a comment. Add support for Z extensions also under this scheme. In order to support these I've had to tweak the multi-letter extension parsing a little. The net result is that error messages printed regarding version numbers are no

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

simoncook planned changes to this revision. simoncook added a comment. With the update to D69987 adding the `Zvqmac` predicate, it seems both the `b` and `v` extensions have Z extensions that also need supporting using this method, I'll update this to also suppo

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

simoncook updated this revision to Diff 242286. simoncook added a comment. Switch to using `Optional` for returning version numbers. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D73891/new/ https://reviews.llvm.org/D73891 Files: clang/include/cl

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

simoncook marked 2 inline comments as done. simoncook added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:50 +static bool isExperimentalExtension(StringRef Ext) { + // Currently 'b' is the only supported experimental extension rogfer0

[PATCH] D71553: [RISCV] Add Clang frontend support for Bitmanip extension

simoncook updated this revision to Diff 242082. simoncook added a comment. Rebase changes on top of experimental feature support (D73891 ) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D71553/new/ https://reviews.ll

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

simoncook updated this revision to Diff 242080. simoncook added a comment. Don't put option in m_riscv_Features_Group, we don't want it being handled like a feature. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D73891/new/ https://reviews.llvm.org/D73891 Files: clang/include/clang/D

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

simoncook created this revision. simoncook added reviewers: asb, lenary, PaoloS, s.egerton. Herald added subscribers: cfe-commits, luismarques, apazos, sameer.abuasal, pzheng, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jr

[PATCH] D54214: [RISCV] Set triple based on -march flag

This revision was automatically updated to reflect the committed changes. Closed by commit rGc00e5cf29d49: [RISCV] Set triple based on -march flag (authored by simoncook). Changed prior to commit: https://reviews.llvm.org/D54214?vs=228261&id=229784#toc Repository: rG LLVM Github Monorepo CH

[PATCH] D54214: [RISCV] Set triple based on -march flag

simoncook updated this revision to Diff 228261. simoncook added a comment. Rebase. @lenary Following the discussion regarding D69383 , I think it's best for now to keep the logic just keeping `-march` directly, rather than using `getRISCVArch`. I think in the c

[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

simoncook added a comment. I have a question about backwards compatibility with this patch. Clang 9 has shipped with rvXXg/etc defaulting to ilp32/lp64 ABI, and no march meaning rvXXi, with users having built objects with those defaults. When Clang 10 ships, users they now need to always use a

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

simoncook added a comment. In D67185#1718459 , @luismarques wrote: > @simoncook: your commit doesn't include handling the case of TLS lowering > when `-ffixed-x4` is used. I looked at this, and did start writing the patch that covers the use of TP/X4 f

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

This revision was automatically updated to reflect the committed changes. Closed by commit rGaed9d6d64a38: [RISCV] Add support for -ffixed-xX flags (authored by simoncook). Changed prior to commit: https://reviews.llvm.org/D67185?vs=223005&id=226081#toc Repository: rG LLVM Github Monorepo C

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

simoncook added a comment. In D67185#1708177 , @asb wrote: > In D67185#1707849 , @lenary wrote: > > > Note, D68862 is in-progress at the > > moment, which is related to this patch.

[PATCH] D54214: [RISCV] Set triple based on -march flag

simoncook added a comment. Herald added a subscriber: pzheng. Ping, before I rebased this did anyone have any other thoughts on flag precedence? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54214/new/ https://reviews.llvm.org/D54214 __

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

simoncook marked 2 inline comments as done. simoncook added inline comments. Comment at: clang/include/clang/Driver/Options.td:2224 HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">; -foreach i = {1-7,9-15,18,20-28} in - def ffixed_x#i : Flag<["-"], "ffixe

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

simoncook updated this revision to Diff 223005. simoncook added a reviewer: luismarques. simoncook added a comment. Rebase on top of tree, add @luismarques as reviewer Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67185/new/ https://reviews.llvm.or

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

simoncook updated this revision to Diff 220876. simoncook added a comment. Update to reflect comments about the fact registers are explicitly reserved. In addition to @lenary 's suggested change, I renamed `isReservedReg` to note the check that we are checking if its a user provided reservation.

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

simoncook updated this revision to Diff 219068. simoncook edited the summary of this revision. simoncook added a comment. Update based on initial feedback/going down the providing error route. Unlike AArch64, which provides an error if a function tries to call a function with arguments and any o

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

simoncook added a comment. For added context, I have gone and double-checked with GCC's implementation both for AArch64 and RISC-V and for registers used by the calling convention the compiler will still use them for argument passing and return values, but otherwise won't use it for any tempora

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

simoncook planned changes to this revision. simoncook added a comment. Thanks for the feedback. I will improve the test so it more reliably tests what it intends to. With regards to behaviour surrounding things such as argument registers, before submitting I checked what the riscv port of GCC d

[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

simoncook created this revision. simoncook added reviewers: asb, lenary. Herald added subscribers: llvm-commits, cfe-commits, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, ni

[PATCH] D54214: [RISCV] Set triple based on -march flag

simoncook added a comment. In D54214#1609967 , @lenary wrote: > What happens if I pass `clang -march=rv32i -target riscv64-unknown-elf`? > Should we care about the ordering of `-march` vs `-target`? Currently this patch makes the output be generated for

[PATCH] D54214: [RISCV] Set triple based on -march flag

simoncook updated this revision to Diff 212772. simoncook added a comment. Herald added subscribers: s.egerton, lenary, Jim, benna, psnobl. Herald added a project: clang. Rebase on top of tree. I've noticed that without this flag calling riscv32-unknown-elf-clang -march=rv64i will still produce

[PATCH] D64737: RISCV: Add support for floating point registers in inlineasm

This revision was automatically updated to reflect the committed changes. Closed by commit rL367399: [RISCV] Add support for floating point registers in inlineasm (authored by simoncook, committed by ). Herald added subscribers: llvm-commits, s.egerton. Herald added a project: LLVM. Changed prior

[PATCH] D64737: RISCV: Add support for floating point registers in inlineasm

simoncook added a comment. As an aside, I've noticed a codegen issue when using floating point clobber lists, resulting in the implicit-defs not being added to INLINEASM instructions. I'm working on a fix for that now and will submit a second patch shortly. Repository: rG LLVM Github Monore

[PATCH] D64737: RISCV: Add support for floating point registers in inlineasm

simoncook created this revision. simoncook added a reviewer: asb. Herald added subscribers: cfe-commits, lenary, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, johnrusso, rbar.

[PATCH] D57497: [RISCV] Passing -G value to RISCV backend

simoncook added a comment. As this mllvm option only affects the creation of ELF objects, do we also need to add a similar option for the LTO case, as the -G value would have no effect otherwise? Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57497/new/ https://

[PATCH] D54214: [RISCV] Set triple based on -march flag

simoncook created this revision. simoncook added a reviewer: asb. Herald added subscribers: cfe-commits, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, johnrusso, rbar. For RISC-V the valu

[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

simoncook accepted this revision. simoncook added a comment. This revision is now accepted and ready to land. My tests now look better, there are a couple of failures, but this seems to be a bug in newlib, rather than with clang/this patch (the bug was masked before as we would have been pulling

[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

simoncook requested changes to this revision. simoncook added a comment. This revision now requires changes to proceed. Herald added a subscriber: PkmX. I've tested this, regression tests involving linking now mostly pass as crt0 can now be found, but it seems that system headers are still being

[PATCH] D46822: [RISCV] Add driver for riscv32-unknown-elf baremetal target

simoncook added a comment. It seems the ability to link objects has been broken by this change. As an example from our nightly tests: Executing on host: riscv32-unknown-elf-clang /data/jenkins/workspace/riscv32-llvm-gcc/gcc-tests/gcc/testsuite/gcc.c-torture/execute/20080502-1.c -march=rv32g

[PATCH] D48412: [RISCV] Support for __attribute__((interrupt))

simoncook added a comment. I think this should also cover mismatched arguments if the attribute appears several times, and reject/warn about the attribute combination in these cases. For example, `__attribute__((interrupt("machine"))) __attribute__((interrupt("user"))) void foo() {}` is accepte