[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

jyknight added a comment. Herald added a subscriber: StephenFan. Herald added a project: All. What's the status of this? Did the GCC proposal go anywhere? I'd be happy to see this move forward if you're also pushing it on the GCC side. Comment at:

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

anirudhp added a comment. In D105142#2862592 , @jyknight wrote: > This code doesn't handle multiple alternatives in a constraint. > > E.g. `"={eax}{ebx}"` or `"={eax}{ebx},m"`. > > See the GCC docs for the C-level syntax >

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

theraven added a comment. In D105142#2850247 , @anirudhp wrote: > In D105142#2849835 , @theraven > wrote: > >> The code looks fine but it would be good to see some docs along with it. >> We're currently

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

jyknight added a comment. This code doesn't handle multiple alternatives in a constraint. E.g. `"={eax}{ebx}"` or `"={eax}{ebx},m"`. See the GCC docs for the C-level syntax https://gcc.gnu.org/onlinedocs/gcc/Multi-Alternative.html#Multi-Alternative and LLVM IR docs for the IR syntax:

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

anirudhp added a comment. @MaskRay Could you please look at the latest changeset, I have added your example as a separate test case for the x86 target. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105142/new/ https://reviews.llvm.org/D105142

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

anirudhp updated this revision to Diff 356968. anirudhp added a comment. - Something went wrong with the previous time updating the diff. I'm not too sure, but I'm just doing it again, and this time the it looks a lot better. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

anirudhp updated this revision to Diff 356961. anirudhp added a comment. - Disable constraint simplification when you already have a constraint of the form {...}. Constraint simplification is usually done character by character, with different targets having different implementations. -

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

anirudhp added a comment. In D105142#2860885 , @MaskRay wrote: > This is great. > > unsigned long foo(unsigned long addr, unsigned long a0, > unsigned long a1, unsigned long a2, > unsigned long a3, unsigned long

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

MaskRay added subscribers: rampitec, arsenm. MaskRay added a comment. This is great. unsigned long foo(unsigned long addr, unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, unsigned long a4, unsigned long a5) {

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

anirudhp added a comment. In D105142#2849835 , @theraven wrote: > The code looks fine but it would be good to see some docs along with it. > We're currently missing docs on inline assembly entirely and the GCC ones are > somewhat... opaque when it

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

theraven added a comment. The code looks fine but it would be good to see some docs along with it. We're currently missing docs on inline assembly entirely and the GCC ones are somewhat... opaque when it comes to describing how constraints work. Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

anirudhp updated this revision to Diff 355332. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105142/new/ https://reviews.llvm.org/D105142 Files: clang/include/clang/Basic/TargetInfo.h clang/lib/Basic/TargetInfo.cpp

[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

anirudhp created this revision. Herald added subscribers: pengfei, jfb, tpr. anirudhp requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. - Relevant RFCs posted here https://lists.llvm.org/pipermail/llvm-dev/2021-June/151370.html