[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

pengfei added a comment. Thanks @vtjnash for the information! Comments on https://github.com/JuliaLang/julia/issues/44829 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105263/new/ https://reviews.llvm.org/D105263 _

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

vtjnash added a comment. Herald added a subscriber: StephenFan. Herald added a project: All. I was tracking back a recent ABI break (also failing now in gcc 12, so maybe this irregularity is intentional), and was concerned that this commit is observed to cause the platform ABI to change dependin

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

pengfei added inline comments. Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:4159 +defm VMOVSHZ : avx512_move_scalar<"vmovsh", X86Movsh, X86vzload16, f16x_info, + [HasFP16]>, + VEX_LIG, T_MAP5XS, EVEX_CD8<16, C

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105263/new/ https://reviews.llvm.org/D105263 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added inline comments. Comment at: clang/docs/LanguageExtensions.rst:599 * SPIR +* X86 Might be worth mentioning that it requires AVX512FP16 here Comment at: clang/lib/CodeGen/TargetInfo.cpp:2817 Current = SSE; +} els

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

LuoYuanke accepted this revision. LuoYuanke added a comment. This revision is now accepted and ready to land. LGTM, but may wait 1 or 2 days for the comments from others. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105263/new/ https://reviews.llv

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

pengfei added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:3471 + ContainsFloatAtOffset(IRType, IROffset + 4, getDataLayout())) +return llvm::FixedVectorType::get(llvm::Type::getHalfTy(getVMContext()), 4); + LuoYuanke wrote: > For 2 flo

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

LuoYuanke added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:3471 + ContainsFloatAtOffset(IRType, IROffset + 4, getDataLayout())) +return llvm::FixedVectorType::get(llvm::Type::getHalfTy(getVMContext()), 4); + For 2 float, return <2xflo

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

LuoYuanke added inline comments. Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:4478 + let Predicates = [HasFP16] in { +def VMOVSHZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), +(ins VR128X:$src1, VR128X:$src2), pengfei wrote: > craig.toppe

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

pengfei added inline comments. Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:4478 + let Predicates = [HasFP16] in { +def VMOVSHZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), +(ins VR128X:$src1, VR128X:$src2), craig.topper wrote: > pengfei

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:4478 + let Predicates = [HasFP16] in { +def VMOVSHZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), +(ins VR128X:$src1, VR128X:$src2), pengfei wrote: > LuoYuank

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

pengfei marked 7 inline comments as done. pengfei added a comment. Thanks Yuanke. Comment at: clang/lib/Headers/avx512fp16intrin.h:292 + + return (__m128h)__builtin_ia32_loadsh128_mask((__v8hf *)__A, src, __U & 1); +} LuoYuanke wrote: > Just be curious, why no

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

LuoYuanke added inline comments. Comment at: llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll:374 +; SSE-NEXT:movl %edi, %ebp +; SSE-NEXT:movzwl %bx, %edi ; SSE-NEXT:callq __gnu_h2f_ieee@PLT Why this test case changes? Shall we add -mattr=+avx512fp16

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

LuoYuanke added inline comments. Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:82 + PatFrags ScalarIntMemFrags = !if (!eq (EltTypeName, "f16"), + !cast("sse_load_f16"), + !if (!eq (EltTypeName, "f32"), -

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

LuoYuanke added inline comments. Comment at: llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp:801 // 0b00010: implied 0F 38 leading opcode bytes // 0b00011: implied 0F 3A leading opcode bytes // 0b00100-0b1: Reserved for future use Add commen

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

LuoYuanke added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:3405 +/// half member at the specified offset. For example, {int,{half}} has a +/// float at offset 4. It is conservatively correct for this routine to return +/// false. float -> hal

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

pengfei added inline comments. Comment at: clang/lib/Headers/avx512vlfp16intrin.h:74 +static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_abs_ph(__m256h __A) { + return (__m256h)_mm256_and_epi32(_mm256_set1_epi32(0x7FFF7FFF), (__m256i)__A); +} craig.topper w

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:254 +/// Constructs a 512-bit floating-point vector of [32 x half] from a +///128-bit floating-point vector of [16 x half]. The lower 256 bits +///contain the value of the source vector.

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

pengfei added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:38 + +static __inline__ _Float16 __DEFAULT_FN_ATTRS512 _mm512_cvtsh_h(__m512h __a) { + return __a[0]; RKSimon wrote: > pengfei wrote: > > RKSimon wrote: > > > I realize its a lot of

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

RKSimon added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:38 + +static __inline__ _Float16 __DEFAULT_FN_ATTRS512 _mm512_cvtsh_h(__m512h __a) { + return __a[0]; pengfei wrote: > RKSimon wrote: > > I realize its a lot of work, but is there an

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86Subtarget.h:748 bool hasVLX() const { return HasVLX; } + bool hasFP16() const { return HasFP16; } bool hasPKU() const { return HasPKU; } pengfei wrote: > RKSimon wrote: > > I'm a little

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

pengfei added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:38 + +static __inline__ _Float16 __DEFAULT_FN_ATTRS512 _mm512_cvtsh_h(__m512h __a) { + return __a[0]; RKSimon wrote: > I realize its a lot of work, but is there any chance that we co

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

RKSimon added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:38 + +static __inline__ _Float16 __DEFAULT_FN_ATTRS512 _mm512_cvtsh_h(__m512h __a) { + return __a[0]; I realize its a lot of work, but is there any chance that we could get doxygen

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

pengfei added inline comments. Comment at: clang/test/CodeGen/X86/avx512fp16-complex.c:1 +// RUN: %clang_cc1 %s -O0 -fno-experimental-new-pass-manager -emit-llvm -triple x86_64-unknown-unknown -target-feature +avx512fp16 -o - | FileCheck %s --check-prefix=X86 +

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:51 + +static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_undefined_ph() { + return (__m256h)__builtin_ia32_undef256(); I think this should be `_mm256_undefined_ph(void)`

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

pengfei added a comment. In D105263#2852295 , @tschuett wrote: > Could you add a link to a reference? Done. Thanks for reminding. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105263/new/ https://reviews.

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

tschuett added a comment. Could you add a link to a reference? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105263/new/ https://reviews.llvm.org/D105263 ___ cfe-commits mailing list cfe-commits@lists.ll