[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-25 Thread Craig Topper via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rGe2b7aabb57d5: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.ll

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-24 Thread Zakk Chen via Phabricator via cfe-commits
khchen added a comment. LGTM, too. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112102/new/ https://reviews.llvm.org/D112102 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-22 Thread Roger Ferrer Ibanez via Phabricator via cfe-commits
rogfer01 added a comment. Looks good to me too. Thanks a lot @craig.topper ! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112102/new/ https://reviews.llvm.org/D112102 ___ cfe-commits mailing list cfe-co

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-22 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai added a comment. It looks good to me. Wait for others' opinions. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112102/new/ https://reviews.llvm.org/D112102 ___ cfe-commits mailing list cfe-comm

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-20 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai added a comment. In D112102#3075400 , @craig.topper wrote: > In D112102#3074656 , @frasercrmck > wrote: > >> Minor typo in the description: `differnet` >> >> Does this help with compile times, binary s

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-20 Thread Craig Topper via Phabricator via cfe-commits
craig.topper updated this revision to Diff 380982. craig.topper added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112102/new/ https://reviews.llvm.org/D112102 Files: clang/include/clang/Basic/riscv_vector.td clang/lib/Sema/

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-20 Thread Craig Topper via Phabricator via cfe-commits
craig.topper added a comment. In D112102#3074656 , @frasercrmck wrote: > Minor typo in the description: `differnet` > > Does this help with compile times, binary sizes, etc? This reduces the clang binary size by 2.34 megabytes according to my local rel

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-20 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai added a comment. In D112102#3074656 , @frasercrmck wrote: > Minor typo in the description: `differnet` > > Does this help with compile times, binary sizes, etc? After this patch, we may be able to consider removing all type ending C APIs. Oth

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-20 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll:1358 +; CHECK-NEXT:vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT:vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT:ret frasercrmck wrote: > HsiangKai wrote: > > vmerge.vv

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-20 Thread Zakk Chen via Phabricator via cfe-commits
khchen added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:120 // type transformer (say "vv") each of the types is separated with an // underscore as in "__builtin_rvv_foo_i32m1_i32m1". // nit: we need to update this comment. Reposit

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-20 Thread Fraser Cormack via Phabricator via cfe-commits
frasercrmck added a comment. Minor typo in the description: `differnet` Does this help with compile times, binary sizes, etc? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112102/new/ https://reviews.llvm.org/D112102 _

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-20 Thread Fraser Cormack via Phabricator via cfe-commits
frasercrmck added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll:1358 +; CHECK-NEXT:vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT:vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT:ret HsiangKai wrote: > vmerge.vvm is for integer vect

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-20 Thread Hsiangkai Wang via Phabricator via cfe-commits
HsiangKai added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll:1358 +; CHECK-NEXT:vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT:vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT:ret vmerge.vvm is for integer vectors, doesn't it? Why

[PATCH] D112102: [RISCV] Reduce the number of RISCV vector builtins by an order of magnitude.

2021-10-19 Thread Craig Topper via Phabricator via cfe-commits
craig.topper created this revision. craig.topper added reviewers: khchen, kito-cheng, arcbbb, HsiangKai, evandro, MaskRay, aeubanks, nikic. Herald added subscribers: achieveartificialintelligence, StephenFan, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl,