[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

2019-09-16 Thread Kerry McLaughlin via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes. Closed by commit rL371967: [SVE][Inline-Asm] Add constraints for SVE predicate registers (authored by kmclaughlin, committed by ). Changed prior to commit: https://reviews.llvm.org/D66524?vs=219526=220299#toc

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

2019-09-16 Thread Diana Picus via Phabricator via cfe-commits
rovka accepted this revision. rovka added a comment. This revision is now accepted and ready to land. I think all the outstanding comments have been addressed. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66524/new/ https://reviews.llvm.org/D66524

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

2019-09-10 Thread Kerry McLaughlin via Phabricator via cfe-commits
kmclaughlin marked 3 inline comments as done. kmclaughlin added inline comments. Comment at: docs/LangRef.rst:3818 +- ``Upl``: One of the low eight SVE predicate registers (P0 to P7) +- ``Upa``: Any of the SVE predicate registers (P0 to P15) greened wrote: >

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

2019-09-10 Thread Kerry McLaughlin via Phabricator via cfe-commits
kmclaughlin updated this revision to Diff 219526. kmclaughlin added a comment. - Renamed the //isPredicateConstraint// function to //parsePredicateConstraint// - Added more thorough checks to the tests in aarch64-sve-asm.ll CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66524/new/

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

2019-09-03 Thread David Greene via Phabricator via cfe-commits
greened added inline comments. Comment at: docs/LangRef.rst:3818 +- ``Upl``: One of the low eight SVE predicate registers (P0 to P7) +- ``Upa``: Any of the SVE predicate registers (P0 to P15) What do these names mean? " predicate lower|all?" I see they are

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

2019-09-02 Thread Diana Picus via Phabricator via cfe-commits
rovka added a comment. Just some drive-by suggestions :) Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:5747 + +PredicateConstraint isPredicateConstraint(StringRef Constraint) { + PredicateConstraint P = PredicateConstraint::Invalid; Nit: I think get-

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

2019-08-30 Thread Kerry McLaughlin via Phabricator via cfe-commits
kmclaughlin updated this revision to Diff 218071. kmclaughlin added a comment. - Added isPredicateConstraint function to AArch64ISelLowering.cpp, which returns Upl, Upa or Invalid. This is used to replace some repeated checks of the predicate type - Minor changes to InlineAsm.cpp CHANGES

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

2019-08-21 Thread Sander de Smalen via Phabricator via cfe-commits
sdesmalen added inline comments. Comment at: lib/IR/InlineAsm.cpp:188 + unsigned char C = static_cast(*I); + assert(isdigit(C) && "Not a single digit!"); + int N = C - '0'; `"Expected a digit"` seems more appropriate, since this code is only

[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

2019-08-21 Thread Kerry McLaughlin via Phabricator via cfe-commits
kmclaughlin created this revision. kmclaughlin added reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov, cameron.mcinally, greened. Herald added subscribers: psnobl, rkruppe, tschuett, javed.absar. Herald added a reviewer: rengolin. Herald added a project: LLVM. kmclaughlin added a