[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

Yi-Hong.Lyu added a comment. Seem this commit broke buildbot http://lab.llvm.org:8011/builders/ppc64le-lld-multistage-test/builds/6881 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68877/new/ https://reviews.llvm.org/D68877

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

This revision was automatically updated to reflect the committed changes. Closed by commit rGda720a38b9f2: [AArch64][SVE] Implement masked load intrinsics (authored by kmclaughlin). Changed prior to commit: https://reviews.llvm.org/D68877?vs=226123=226628#toc Repository: rG LLVM Github

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

dmgreen accepted this revision. dmgreen added a comment. This revision is now accepted and ready to land. In D68877#1718729 , @kmclaughlin wrote: > There is not yet support for vector selects, so for this patch the intention > was that any passthru which

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

kmclaughlin marked an inline comment as done. kmclaughlin added a comment. In D68877#1717820 , @dmgreen wrote: > I'm not sure if there is support yet for vector selects in the SVE codegen? There is not yet support for vector selects, so for this patch

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

kmclaughlin updated this revision to Diff 226123. kmclaughlin added a comment. - Removed unnecessary pseudo from SVEInstrFormats.td CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68877/new/ https://reviews.llvm.org/D68877 Files: llvm/include/llvm/CodeGen/SelectionDAG.h

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

dmgreen added a comment. Thanks! It looks like the only supported parameter of the PassThru here is a splat of 0 or undef. This might get in the way of IR level optimisation that could try to producing a masked load with different passthru, which would then fail to select. The ARM backed

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

kmclaughlin marked 4 inline comments as done. kmclaughlin added a comment. Thanks for reviewing this, @dmgreen! I have updated the patch to make use of the changes to DAGCombine introduced by D68337 . Comment at:

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

kmclaughlin updated this revision to Diff 225900. kmclaughlin edited the summary of this revision. kmclaughlin added a comment. - Rebased patch, removed extra sext & zext combine from DAGCombine which are no longer necessary - Added isVectorLoadExtDesirable to AArch64ISelLowering - Added more

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

dmgreen added subscribers: samparker, dmgreen. dmgreen added a comment. Sam has been looking at extending masked loads and stores in D68337 and related patches. There looks like there would be some overlap with this, especially in the target independent parts.

[PATCH] D68877: [AArch64][SVE] Implement masked load intrinsics

kmclaughlin created this revision. kmclaughlin added reviewers: huntergr, rovka, greened. Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added a project: LLVM. kmclaughlin added a parent revision: D47775: [AArch64][SVE] Add SPLAT_VECTOR ISD Node. Adds