This revision was automatically updated to reflect the committed changes.
Closed by commit rGcdcc4f2a44b5: [AArch64][SVE] Add intrinsic for non-faulting
loads (authored by kmclaughlin).
Changed prior to commit:
https://reviews.llvm.org/D71698?vs=239144=239531#toc
Repository:
rG LLVM Github
sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.
LGTM [with the caveat that we need to revisit the modelling of the `FFR`
register and get rid fo the `PseudoInstExpansion` at a later point, as
discussed during the previous sync-up
kmclaughlin updated this revision to Diff 239144.
kmclaughlin added a comment.
- Some minor changes to performSignExtendInRegCombine to address comments from
@sdesmalen
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Files:
sdesmalen added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12460
- if ((SignExtSrcVT != GLD1SrcMemVT) || !Src.hasOneUse())
+ unsigned OpNum = NewOpc == AArch64ISD::LDNF1S ? 3 : 4;
+ EVT LD1SrcMemVT = cast(Src->getOperand(OpNum))->getVT();
kmclaughlin marked 5 inline comments as done.
kmclaughlin added a comment.
Thanks for your suggestions, @andwar!
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kmclaughlin updated this revision to Diff 237906.
kmclaughlin added a comment.
- Rebased patch
- Updated comments and extended getSVEContainerType to handle nxv8i16 & nxv16i8
CHANGES SINCE LAST ACTION
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Files:
efriedma added inline comments.
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:5333
+ // We need a layer of indirection because early machine code passes balk at
+ // physical register (i.e. FFR) uses that have no previous definition.
+ let hasSideEffects = 1,
sdesmalen added inline comments.
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:5333
+ // We need a layer of indirection because early machine code passes balk at
+ // physical register (i.e. FFR) uses that have no previous definition.
+ let hasSideEffects = 1,
andwar added inline comments.
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9998
+
// GLD1* instructions perform an implicit zero-extend, which makes them
// perfect candidates for combining.
Could you replace `GLD1*` with `Load`? I believe
efriedma added inline comments.
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:5333
+ // We need a layer of indirection because early machine code passes balk at
+ // physical register (i.e. FFR) uses that have no previous definition.
+ let hasSideEffects = 1,
kmclaughlin added inline comments.
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:5333
+ // We need a layer of indirection because early machine code passes balk at
+ // physical register (i.e. FFR) uses that have no previous definition.
+ let hasSideEffects = 1,
efriedma added inline comments.
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:5333
+ // We need a layer of indirection because early machine code passes balk at
+ // physical register (i.e. FFR) uses that have no previous definition.
+ let hasSideEffects = 1,
kmclaughlin created this revision.
kmclaughlin added reviewers: sdesmalen, efriedma, andwar, dancgr, mgudim.
Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
This patch adds the llvm.aarch64.sve.ldnf1
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