[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)

https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)

https://github.com/eopXD edited https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)

https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67018 >From dc77e5c7bca87badecc314b24cab4c10be0e02fa Mon Sep 17 00:00:00 2001 From: eopXD Date: Thu, 21 Sep 2023 06:34:57 -0700 Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline

[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)

topperc wrote: Does this mean the backend register allocation will pick a large LMUL register the same size as the whole tuple and force the register to be overly aligned? For example an lmul=1 seg2 tuple can use v0+v1, or v1+v2, or v2+v3, etc. But lmul=2 can only use v0+v1, v2+v3, v4+v5, etc.

[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)

eopXD wrote: > Does this mean the backend register allocation will pick a large LMUL > register the same size as the whole tuple and force the register to be overly > aligned? For example an lmul=1 seg2 tuple can use v0+v1, or v1+v2, or v2+v3, > etc. But lmul=2 can only use v0+v1, v2+v3, v4+v5

[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)

@@ -2524,11 +2551,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) { ResultRegIsFlagReg.push_back(IsFlagReg); llvm::Type *Ty = ConvertTypeForMem(QTy); + ResultTruncRegTypes.push_back(Ty); + + // Expressing the type as a structure in inline asm ca

[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)

https://github.com/eopXD updated https://github.com/llvm/llvm-project/pull/67018 >From 6f232ccd6dd273b9eecec7f583877a3a5a3696c3 Mon Sep 17 00:00:00 2001 From: eopXD Date: Thu, 21 Sep 2023 06:34:57 -0700 Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline

[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)

@@ -2524,11 +2551,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) { ResultRegIsFlagReg.push_back(IsFlagReg); llvm::Type *Ty = ConvertTypeForMem(QTy); + ResultTruncRegTypes.push_back(Ty); + + // Expressing the type as a structure in inline asm ca

[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)

https://github.com/eopXD resolved https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)

eopXD wrote: Change: Updated the approach to get pass inline asm verifications and handle them correctly under `EmitAsmStores`. https://github.com/llvm/llvm-project/pull/67018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.