dtcxzyw wrote:
Rebased on top of #70241.
https://github.com/llvm/llvm-project/pull/70232
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70232
>From b34055dca42c23682bb9f0e9e022f17e9dbf2aca Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 28 Oct 2023 20:46:37 +0800
Subject: [PATCH] [RISCV] Add sched model for XiangShan-NanHu
Co-authored-by: SFor
@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
dtcxzyw wrote:
> Can you separate out the basic processor definition (using NoSchedModel), and
> a patch which adds the scheduling model? We can at least get the processor
> definition landed while we iterate on the scheduling related pieces.
>
> edit: For clarity, I'm requesting that the basi
preames wrote:
Can you separate out the basic processor definition (using NoSchedModel), and a
patch which adds the scheduling model? We can at least get the processor
definition landed while we iterate on the scheduling related pieces.
https://github.com/llvm/llvm-project/pull/70232
__
@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
} // Predicates = [HasStdExtF]
foreach Ext = FExts in {
- let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+ let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {
-
@@ -936,7 +936,9 @@ def : ReadAdvance;
def : ReadAdvance;
def : ReadAdvance;
def : ReadAdvance;
+def : ReadAdvance;
topperc wrote:
Please make FMA16 consistent
https://github.com/llvm/llvm-project/pull/70232
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@@ -78,7 +78,7 @@ def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>;
} // Predicates = [HasStdExtD]
foreach Ext = DExts in {
- let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in {
+ let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64Addend] in {
---
@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
} // Predicates = [HasStdExtF]
foreach Ext = FExts in {
- let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+ let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {
-
llvmbot wrote:
@llvm/pr-subscribers-clang-driver
Author: Yingwei Zheng (dtcxzyw)
Changes
[XiangShan](https://github.com/OpenXiangShan/XiangShan) is an open-source
high-performance RISC-V processor.
This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of the
XiangShan pr
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/70232
[XiangShan](https://github.com/OpenXiangShan/XiangShan) is an open-source
high-performance RISC-V processor.
This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of the
XiangShan processor seri
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