[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

https://github.com/mgudim closed https://github.com/llvm/llvm-project/pull/65535 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

michaelmaitland wrote: > > I think you can drop the merge commit using `git rebase -i`. You may have > > to pass `--rebase-merges` to have the ability to drop the merge commit. > > Then you can pull upstream and `git rebase upstream/main`. > > Thanks Michael, I tried but messed it up (I see mo

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

mgudim wrote: > I think you can drop the merge commit using `git rebase -i`. You may have to > pass `--rebase-merges` to have the ability to drop the merge commit. Then you > can pull upstream and `git rebase upstream/main`. Thanks Michael, I tried but messed it up (I see more changes than I i

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

https://github.com/mgudim updated https://github.com/llvm/llvm-project/pull/65535 >From 8dff19fbb00ce7dcd818eb851601b36a7cdeea42 Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Wed, 6 Sep 2023 17:15:56 -0400 Subject: [PATCH 1/2] [RISCV] Added definition of Ventana veyron-v1 processor. ---

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

mgudim wrote: > > [Merge branch 'llvm:main' into > > mgudim_veyron_def](https://github.com/llvm/llvm-project/pull/65535/commits/454b41eea50a3583ab5c29bffbd46bcd633b) > > The [LLVM GitHub User Guide](https://llvm.org/docs//GitHub.html) recommends > to rebase on main instead of merge main.

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

https://github.com/mgudim updated https://github.com/llvm/llvm-project/pull/65535 >From d1ba27988840703b9a7a12ad48ecfb282752e7e2 Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Wed, 6 Sep 2023 17:15:56 -0400 Subject: [PATCH 1/2] [RISCV] Added definition of Ventana veyron-v1 processor. ---

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

https://github.com/mgudim updated https://github.com/llvm/llvm-project/pull/65535 >From d1ba27988840703b9a7a12ad48ecfb282752e7e2 Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Wed, 6 Sep 2023 17:15:56 -0400 Subject: [PATCH 1/2] [RISCV] Added definition of Ventana veyron-v1 processor. ---

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

https://github.com/mgudim updated https://github.com/llvm/llvm-project/pull/65535: >From d1ba27988840703b9a7a12ad48ecfb282752e7e2 Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Wed, 6 Sep 2023 17:15:56 -0400 Subject: [PATCH] [RISCV] Added definition of Ventana veyron-v1 processor. --- cla

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

@@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

@@ -93,4 +93,4 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

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[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

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[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

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[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

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[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

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[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

https://github.com/mgudim created https://github.com/llvm/llvm-project/pull/65535: None >From 6529eb1ad2a4d5922c8a66d3a11514b5c406eac0 Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Wed, 6 Sep 2023 17:15:56 -0400 Subject: [PATCH] [RISCV] Added definition of Ventana veyron-v1 processor. --

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

https://github.com/mgudim review_requested https://github.com/llvm/llvm-project/pull/65535 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Added definition of Ventana veyron-v1 processor. (PR #65535)

https://github.com/mgudim review_requested https://github.com/llvm/llvm-project/pull/65535 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits