@@ -4850,6 +4852,93 @@ SDValue AArch64TargetLowering::getPStateSM(SelectionDAG
&DAG, SDValue Chain,
Mask);
}
+// Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
sdesmalen-arm wrote:
```suggestion
// Lower an SME LDR/STR ZA
https://github.com/sdesmalen-arm approved this pull request.
Thanks for all the changes! LGTM with few little nits addressed.
https://github.com/llvm/llvm-project/pull/68565
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https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/68565
>From 83e20904c206980285c4ee9d0227706803147654 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Fri, 6 Oct 2023 17:09:36 +0100
Subject: [PATCH 01/12] [AArch64][SME] Remove immediate argument restriction
for
@@ -4825,6 +4827,113 @@ SDValue AArch64TargetLowering::getPStateSM(SelectionDAG
&DAG, SDValue Chain,
Mask);
}
+// Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+// Case 1: If the vector number (vecnum) is an immediate in range, it gets
+//
@@ -4825,6 +4827,72 @@ SDValue AArch64TargetLowering::getPStateSM(SelectionDAG
&DAG, SDValue Chain,
Mask);
}
+SDValue LowerSMELdrStr(SDValue N, SelectionDAG &DAG, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/68565
>From de07976922782b9dcf5d13d44551b782dc8b3b94 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Fri, 6 Oct 2023 17:09:36 +0100
Subject: [PATCH 1/9] [AArch64][SME] Remove immediate argument restriction for
sv
https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/68565
>From de07976922782b9dcf5d13d44551b782dc8b3b94 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Fri, 6 Oct 2023 17:09:36 +0100
Subject: [PATCH 1/7] [AArch64][SME] Remove immediate argument restriction for
sv
@@ -1741,6 +1742,69 @@ void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N,
unsigned NumVecs,
CurDAG->RemoveDeadNode(N);
}
+void AArch64DAGToDAGISel::SelectSMELdrStrZA(SDNode *N, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/68565
>From de07976922782b9dcf5d13d44551b782dc8b3b94 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Fri, 6 Oct 2023 17:09:36 +0100
Subject: [PATCH 1/6] [AArch64][SME] Remove immediate argument restriction for
sv
@@ -4825,6 +4827,72 @@ SDValue AArch64TargetLowering::getPStateSM(SelectionDAG
&DAG, SDValue Chain,
Mask);
}
+SDValue LowerSMELdrStr(SDValue N, SelectionDAG &DAG, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
@@ -292,23 +292,101 @@ define void @ldr_with_off_16mulvl(ptr %ptr) {
%vscale = call i64 @llvm.vscale.i64()
%mulvl = mul i64 %vscale, 256
%base = getelementptr i8, ptr %ptr, i64 %mulvl
- call void @llvm.aarch64.sme.ldr(i32 16, ptr %base)
+ call void @llvm.aarch64.sme.ldr
https://github.com/efriedma-quic edited
https://github.com/llvm/llvm-project/pull/68565
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https://github.com/efriedma-quic commented:
The resulting code here still isn't great quality for the case where the
constant isn't folded. Maybe worth considering doing the lowering earlier
(DAGCombine? Maybe even a late IR optimization?), so the lowered arithmetic
can be optimized.
https:
SamTebbs33 wrote:
I've changed the approach to consider immediates outside of 0-15 and fixed the
issue of the tile slice not being updated. Please let me know what you think.
https://github.com/llvm/llvm-project/pull/68565
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https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/68565
>From de07976922782b9dcf5d13d44551b782dc8b3b94 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Fri, 6 Oct 2023 17:09:36 +0100
Subject: [PATCH 1/5] [AArch64][SME] Remove immediate argument restriction for
sv
https://github.com/SamTebbs33 edited
https://github.com/llvm/llvm-project/pull/68565
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@@ -1741,6 +1742,54 @@ void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N,
unsigned NumVecs,
CurDAG->RemoveDeadNode(N);
}
+void AArch64DAGToDAGISel::SelectSMELdrStrZA(SDNode *N, bool IsLoad) {
+ // Lower an SME LDR/STR ZA intrinsic to LDR_ZA_PSEUDO or STR_ZA.
+ // If
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