@@ -0,0 +1,592 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+// RUN: %clang_cc1 -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature
+sme-f16f16
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/88553
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https://github.com/CarolineConcatto approved this pull request.
https://github.com/llvm/llvm-project/pull/88553
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@@ -458,6 +458,40 @@ let TargetGuard = "sme2,sme-f64f64" in {
def SVMLS_LANE_VG1x4_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x4", "vm4di", "d",
MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA],
[ImmCheck<3, ImmCheck0_1>]>;
}
+let TargetGuard =
@@ -458,6 +458,40 @@ let TargetGuard = "sme2,sme-f64f64" in {
def SVMLS_LANE_VG1x4_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x4", "vm4di", "d",
MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA],
[ImmCheck<3, ImmCheck0_1>]>;
}
+let TargetGuard =
@@ -0,0 +1,592 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+// RUN: %clang_cc1 -fclang-abi-compat=latest
-triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature
+sme-f16f16
@@ -2461,9 +2461,29 @@ multiclass sme2_multi_vec_array_vg2_index_32b sz, bits<
}
// SME2.1 multi-vec ternary indexed two registers 16-bit
-// SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers
multiclass sme2p1_multi_vec_array_vg2_index_16b sz,
bits<3> op,
@@ -0,0 +1,592 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
CarolineConcatto wrote:
If you change these prototypes to be sme2 like the ACLE we need to change these
run lines to be sme2
@@ -2461,9 +2461,29 @@ multiclass sme2_multi_vec_array_vg2_index_32b sz, bits<
}
// SME2.1 multi-vec ternary indexed two registers 16-bit
-// SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers
multiclass sme2p1_multi_vec_array_vg2_index_16b sz,
bits<3> op,
@@ -2599,6 +2619,28 @@ multiclass sme2p1_multi_vec_array_vg4_index_16b op,
sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, zpr_ty:$Zm,
VectorIndexH:$i), 0>;
}
+// SME2.1 multi-vec ternary indexed four registers 16-bit
+multiclass sme2p1_multi_vec_array_vg4_index_16b op,
+
@@ -0,0 +1,462 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --filter-out "// kill:.*$" --version 4
+; RUN: llc -verify-machineinstrs < %s | FileCheck %s
+
CarolineConcatto wrote:
I believe we can add these tests in
@@ -2599,6 +2619,28 @@ multiclass sme2p1_multi_vec_array_vg4_index_16b op,
sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, zpr_ty:$Zm,
VectorIndexH:$i), 0>;
}
+// SME2.1 multi-vec ternary indexed four registers 16-bit
+multiclass sme2p1_multi_vec_array_vg4_index_16b op,
+
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/88553
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llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Momchil Velikov (momchil-velikov)
Changes
---
Patch is 108.24 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/88553.diff
6 Files Affected:
- (modified)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Momchil Velikov (momchil-velikov)
Changes
---
Patch is 108.24 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/88553.diff
6 Files Affected:
- (modified) clang/include/clang/Basic/arm_sme.td
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