https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/117781
>From e66f451e1db4c321acbfac578fa57f286af2fe27 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Wed, 13 Nov 2024 10:54:16 -0800
Subject: [PATCH 1/4] [HLSL] Implement SV_GroupThreadId semantic
Support SV_Gr
https://github.com/llvm-beanz approved this pull request.
https://github.com/llvm/llvm-project/pull/117781
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lizhengxing wrote:
@sudonatalie
Hello Natalie,
Could you help review this PR when you're available since it will modify your
changes (https://github.com/llvm/llvm-project/pull/82536), Thanks.
https://github.com/llvm/llvm-project/pull/117781
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@@ -2851,7 +2851,21 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
.constrainAllUses(TII, TRI, RBI);
break;
case Intrinsic::spv_thread_id:
-return selectSpvThreadId(ResVReg, ResType, I);
+// The HLSL SV_DispatchThreadID semantic is
https://github.com/tex3d approved this pull request.
I think it's good, with minor nit about unnecessary comments.
https://github.com/llvm/llvm-project/pull/117781
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@@ -2851,7 +2851,21 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
.constrainAllUses(TII, TRI, RBI);
break;
case Intrinsic::spv_thread_id:
-return selectSpvThreadId(ResVReg, ResType, I);
+// The HLSL SV_DispatchThreadID semantic is
@@ -3606,6 +3613,32 @@ bool
SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
return Result && MIB.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
+ const SPIR
@@ -3606,6 +3613,32 @@ bool
SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
return Result && MIB.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
+ const SPIR
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/117781
>From 2941d87dbaf091aa443ad57ce55e98e7bab83d2b Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Wed, 13 Nov 2024 10:54:16 -0800
Subject: [PATCH 1/4] [HLSL] Implement SV_GroupThreadId semantic
Support SV_Gr
@@ -3606,6 +3613,32 @@ bool
SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
return Result && MIB.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
+ const SPIR
https://github.com/lizhengxing edited
https://github.com/llvm/llvm-project/pull/117781
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@@ -3606,6 +3613,32 @@ bool
SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
return Result && MIB.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
+ const SPIR
@@ -3606,6 +3613,32 @@ bool
SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
return Result && MIB.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
+ const SPIR
@@ -3606,6 +3613,32 @@ bool
SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
return Result && MIB.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
+ const SPIR
https://github.com/lizhengxing edited
https://github.com/llvm/llvm-project/pull/117781
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https://github.com/lizhengxing edited
https://github.com/llvm/llvm-project/pull/117781
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@@ -389,6 +389,11 @@ llvm::Value *CGHLSLRuntime::emitInputSemantic(IRBuilder<>
&B,
CGM.getIntrinsic(getThreadIdIntrinsic());
return buildVectorInput(B, ThreadIDIntrinsic, Ty);
}
+ if (D.hasAttr()) {
+llvm::Function *GroupThreadIDIntrinsic =
+CGM.getI
@@ -2,15 +2,18 @@
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-mesh -hlsl-entry CSMain -x
hlsl -finclude-default-header -verify -o - %s
[numthreads(8,8,1)]
-// expected-error@+3 {{attribute 'SV_GroupIndex' is unsupported in 'mesh'
shaders, requires compute}}
-// expect
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/117781
>From 2941d87dbaf091aa443ad57ce55e98e7bab83d2b Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Wed, 13 Nov 2024 10:54:16 -0800
Subject: [PATCH 1/3] [HLSL] Implement SV_GroupThreadId semantic
Support SV_Gr
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