kstoimenov wrote:
@mgoudar FYI I reverted this patch due to sanitizer bot failure.
https://github.com/llvm/llvm-project/pull/134985
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mgoudar wrote:
hi @brad0 I am seeing fails in https://lab.llvm.org/buildbot/#/builders/94 post
this pr merge.
test llvm/test/CodeGen/Mips/msa/arithmetic.ll fails with a crash. I am trying
to reproduce at my side
https://github.com/llvm/llvm-project/pull/134985
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https://github.com/mshockwave approved this pull request.
LGTM, thanks
https://github.com/llvm/llvm-project/pull/134985
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mgoudar wrote:
I added RUN commands for i6500/i6400 msa test to the existing test
test/CodeGen/Mips/msa/arithmetic.ll and deleted new test that was added in the
prev commit.
https://github.com/llvm/llvm-project/pull/134985
https://github.com/mgoudar edited
https://github.com/llvm/llvm-project/pull/134985
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@@ -0,0 +1,724 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips64 -mcpu=i6500 < %s | FileCheck %s --check-prefixes=ALL
+; RUN: llc -mtriple=mips64 -mcpu=i6400 < %s | FileCheck %s --check-prefixes=ALL
mgoud
https://github.com/mgoudar updated
https://github.com/llvm/llvm-project/pull/134985
Rate limit ยท GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Arial,sans-s
@@ -0,0 +1,724 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips64 -mcpu=i6500 < %s | FileCheck %s --check-prefixes=ALL
+; RUN: llc -mtriple=mips64 -mcpu=i6400 < %s | FileCheck %s --check-prefixes=ALL
mshoc
mshockwave wrote:
I just noticed there is already `test/CodeGen/Mips/msa/arithmetic.ll` (which
this file is probably based on), could add additional `RUN` lines to that file
instead, in order to reuse it?
https://github.com/llvm/llvm-project/pull/134985
_
https://github.com/mshockwave edited
https://github.com/llvm/llvm-project/pull/134985
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https://github.com/mshockwave commented:
Sorry I missed the update. I only have some minor comments
https://github.com/llvm/llvm-project/pull/134985
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brad0 wrote:
@mshockwave
https://github.com/llvm/llvm-project/pull/134985
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@@ -0,0 +1,9 @@
+// Check target CPUs are correctly passed.
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck
-check-prefix=MCPU-I6400 %s
+// MCPU-I6400: "-target-cpu" "i6400"
mgoudar wrote:
I modified test to verify abicalls featur
@@ -0,0 +1,69 @@
+; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
mgoudar wrote:
I have enabled MSA feature from driver also when -mcpu i6500/i6400 is
specified. Also I have added codegen test to verify MSA instructions when
i650
https://github.com/mgoudar updated
https://github.com/llvm/llvm-project/pull/134985
>From 36a78bb9fe38781fa8ea126aeae5b7ed48140651 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda
Date: Tue, 1 Apr 2025 12:35:27 +0530
Subject: [PATCH 1/6] [MIPS] Add FeatureMSA to i6400 and i6500 cores
i6400 an
https://github.com/mgoudar updated
https://github.com/llvm/llvm-project/pull/134985
>From 36a78bb9fe38781fa8ea126aeae5b7ed48140651 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda
Date: Tue, 1 Apr 2025 12:35:27 +0530
Subject: [PATCH 1/5] [MIPS] Add FeatureMSA to i6400 and i6500 cores
i6400 an
@@ -0,0 +1,9 @@
+// Check target CPUs are correctly passed.
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck
-check-prefix=MCPU-I6400 %s
+// MCPU-I6400: "-target-cpu" "i6400"
mshockwave wrote:
usually we will check all the features
https://github.com/mgoudar edited
https://github.com/llvm/llvm-project/pull/134985
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@@ -0,0 +1,69 @@
+; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
mgoudar wrote:
I have written driver test mips-cpus.c instead of codegen as you suggested.
https://github.com/llvm/llvm-project/pull/134985
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Mallikarjuna Gouda (mgoudar)
Changes
Enable 'FeatureMSA' for MIPS i6400 and i6500 cpu.
MIPS i6400 and i6500 cores implements MSA (MIPS SIMD ARCHITECTURE) by default.
---
Full diff: https://github.com/llvm/llvm-project/pull/134985.diff
2
llvmbot wrote:
@llvm/pr-subscribers-clang-driver
Author: Mallikarjuna Gouda (mgoudar)
Changes
Enable 'FeatureMSA' for MIPS i6400 and i6500 cpu.
MIPS i6400 and i6500 cores implements MSA (MIPS SIMD ARCHITECTURE) by default.
---
Full diff: https://github.com/llvm/llvm-project/pull/134985.d
https://github.com/mgoudar updated
https://github.com/llvm/llvm-project/pull/134985
>From 36a78bb9fe38781fa8ea126aeae5b7ed48140651 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda
Date: Tue, 1 Apr 2025 12:35:27 +0530
Subject: [PATCH 1/3] [MIPS] Add FeatureMSA to i6400 and i6500 cores
i6400 an
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