[clang] [llvm] [RISCV] Add sifive-p670 processor (PR #79015)

https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/79015 >From 639d404b3b8a8ca7e92160fa8512459be07e631f Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Mon, 22 Jan 2024 07:53:55 -0800 Subject: [PATCH 1/6] [RISCV] Add sifive-p670 processor This is an OOO

[clang] [llvm] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -241,7 +241,17 @@ // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs" // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d" -// + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIF

[clang] [llvm] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -2000,6 +2000,14 @@ bool RISCVTargetLowering::shouldSinkOperands( if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions()) return false; + // Don't sink splat operands if the target prefers it. Some targets requires michaelmaitland wrote: U

[clang] [llvm] [RISCV] Add sifive-p670 processor (PR #79015)

@@ -2000,6 +2000,14 @@ bool RISCVTargetLowering::shouldSinkOperands( if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions()) return false; + // Don't sink splat operands if the target prefers it. Some targets requires topperc wrote: This chan