[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-28 Thread Brendan Dahl via cfe-commits
https://github.com/brendandahl closed https://github.com/llvm/llvm-project/pull/93360 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-28 Thread Heejin Ahn via cfe-commits
https://github.com/aheejin approved this pull request. https://github.com/llvm/llvm-project/pull/93360 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-28 Thread Brendan Dahl via cfe-commits
@@ -1199,6 +1213,7 @@ def : Pat<(v2f64 (froundeven (v2f64 V128:$src))), (NEAREST_F64x2 V128:$src)>; multiclass SIMDBinaryFP baseInst> { defm "" : SIMDBinary; defm "" : SIMDBinary; + defm "" : SIMDBinary; brendandahl wrote: I ended up adding `HalfPrecisi

[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-28 Thread Brendan Dahl via cfe-commits
@@ -152,6 +153,18 @@ def F64x2 : Vec { let prefix = "f64x2"; } +def F16x8 : Vec { + let vt = v8f16; + let int_vt = v8i16; + let lane_vt = f32; + let lane_rc = F32; + let lane_bits = 16; + let lane_idx = LaneIdx8; + let lane_load = int_wasm_loadf16_f32; + let splat = PatFrag<

[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-28 Thread Brendan Dahl via cfe-commits
https://github.com/brendandahl updated https://github.com/llvm/llvm-project/pull/93360 >From c33801afebb6720bc4b51fb4064b59529c40d298 Mon Sep 17 00:00:00 2001 From: Brendan Dahl Date: Thu, 23 May 2024 23:38:51 + Subject: [PATCH 1/2] [WebAssembly] Implement all f16x8 binary instructions. Th

[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-28 Thread Heejin Ahn via cfe-commits
@@ -152,6 +153,18 @@ def F64x2 : Vec { let prefix = "f64x2"; } +def F16x8 : Vec { + let vt = v8f16; + let int_vt = v8i16; + let lane_vt = f32; + let lane_rc = F32; + let lane_bits = 16; + let lane_idx = LaneIdx8; + let lane_load = int_wasm_loadf16_f32; + let splat = PatFrag<

[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-28 Thread Heejin Ahn via cfe-commits
@@ -1199,6 +1213,7 @@ def : Pat<(v2f64 (froundeven (v2f64 V128:$src))), (NEAREST_F64x2 V128:$src)>; multiclass SIMDBinaryFP baseInst> { defm "" : SIMDBinary; defm "" : SIMDBinary; + defm "" : SIMDBinary; aheejin wrote: I understand why it's added, and I

[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-28 Thread Heejin Ahn via cfe-commits
https://github.com/aheejin edited https://github.com/llvm/llvm-project/pull/93360 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-28 Thread Heejin Ahn via cfe-commits
https://github.com/aheejin commented: Now you have commit access! https://github.com/llvm/llvm-project/pull/93360 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-24 Thread Brendan Dahl via cfe-commits
https://github.com/brendandahl edited https://github.com/llvm/llvm-project/pull/93360 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-24 Thread via cfe-commits
llvmbot wrote: @llvm/pr-subscribers-backend-webassembly @llvm/pr-subscribers-clang Author: Brendan Dahl (brendandahl) Changes This reuses most of the code that was created for f32x4 and f64x2 binary instructions and tries to follow how they were implemented. add/sub/mul/div - use regular

[clang] [llvm] [WebAssembly] Implement all f16x8 binary instructions. (PR #93360)

2024-05-24 Thread Brendan Dahl via cfe-commits
https://github.com/brendandahl created https://github.com/llvm/llvm-project/pull/93360 This reuses most of the code that was created for f32x4 and f64x2 binary instructions and tries to follow how they were implemented. add/sub/mul/div - use regular LL instructions min/max - use the minimum/ma