urnathan wrote:
#65742 is committed, so MIPS' TargetInfo will need adjusting to propagate the
unaligned capability. See 7df79ababee8
https://github.com/llvm/llvm-project/pull/85174
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https://github.com/wzssyqa closed
https://github.com/llvm/llvm-project/pull/85174
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https://github.com/llvm/llvm-project/pull/85174
>From 7e1cf74f4fc9271e88b62462ea9a38826fd3ee38 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Thu, 14 Mar 2024 11:48:36 +0800
Subject: [PATCH] MIPS: Support -m(no-)strict-align for r6
MIPSr6 ISA requires
https://github.com/wzssyqa edited
https://github.com/llvm/llvm-project/pull/85174
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>From e75523f5ab1bb58a495afdd30203a0c7c93c7ec4 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Thu, 14 Mar 2024 11:48:36 +0800
Subject: [PATCH] MIPS: Support -m(no-)strict-align for r6
MIPSr6 ISA requires
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 437fcc6eed99694a9f9486d29ead6a3d3275ede9
a74a9bbd2ff2c6589db4c9756cf809c22e98fa64 --
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: YunQiang Su (wzssyqa)
Changes
MIPSr6 ISA requires normal load/store instructions support misunaligned memory
access, while it is not always do so by hardware. On some microarchitectures or
some corner cases it may need support by OS.
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/85174
MIPSr6 ISA requires normal load/store instructions support misunaligned memory
access, while it is not always do so by hardware. On some microarchitectures or
some corner cases it may need support by OS.
Don't
