https://github.com/CarolineConcatto approved this pull request.
https://github.com/llvm/llvm-project/pull/75596
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone,
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1,
ImmCheck2_4_Mul2>]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone,
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1,
ImmCheck2_4_Mul2>]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
@@ -2066,7 +2066,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone, IsStreamingCompatible]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
+let TargetGuard = "(sve2|sme2),b16b16" in {
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Momchil Velikov (momchil-velikov)
Changes
According to the latest update of the ISA
https://developer.arm.com/documentation/ddi0602/2023-09/?lang=en all of the
affected instruction encodings now require
(FEAT_SVE2 or
