[mlir] [clang] [llvm] [AMDGPU] - Add address space for strided buffers (PR #74471)

@@ -864,6 +865,16 @@ supported for the ``amdgcn`` target. (bits `127:96`). The specific interpretation of these fields varies by the target architecture and is detailed in the ISA descriptions. +**Buffer Strided Pointer** + The buffer index pointer is an experimental

[mlir] [clang] [llvm] [AMDGPU] - Add address space for strided buffers (PR #74471)

https://github.com/OutOfCache updated https://github.com/llvm/llvm-project/pull/74471 >From 94ed734c0d8864a08e3b77600dda811040270bd9 Mon Sep 17 00:00:00 2001 From: Jessica Del Date: Tue, 5 Dec 2023 13:45:58 +0100 Subject: [PATCH 1/5] [AMDGPU] - Add address space for strided buffers This is an

[mlir] [clang] [llvm] [AMDGPU] - Add address space for strided buffers (PR #74471)

@@ -864,6 +865,17 @@ supported for the ``amdgcn`` target. (bits `127:96`). The specific interpretation of these fields varies by the target architecture and is detailed in the ISA descriptions. +**Buffer Strided Pointer** + The buffer index pointer is an experimental

[mlir] [clang] [llvm] [AMDGPU] - Add address space for strided buffers (PR #74471)

@@ -1,7 +1,7 @@ ; RUN: opt -S -mtriple=amdgcn-- -passes=load-store-vectorizer < %s | FileCheck -check-prefix=OPT %s nhaehnle wrote: I think it's fine. It's still a kind of buffer fat pointer in a sense. https://github.com/llvm/llvm-project/pull/74471

[mlir] [clang] [llvm] [AMDGPU] - Add address space for strided buffers (PR #74471)

https://github.com/nhaehnle edited https://github.com/llvm/llvm-project/pull/74471 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits