[clang] [llvm] [LV] Mask off possibly aliasing vector lanes (PR #100579)

@@ -2725,9 +2725,17 @@ class VPAliasLaneMaskRecipe : public VPSingleDefRecipe { /// Get the VPValue* for the pointer being read from VPValue *getSourceValue() const { return getOperand(0); } + // Get the size of the element(s) accessed by the pointers + unsigned getAcces

[clang] [llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

@@ -567,6 +567,9 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM: return "histogram"; + case ISD::EXPERIMENTAL_ALIAS_LANE_MASK: +return "alias_mask"; SamTebbs33 wrote: Done. https://g

[clang] [llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

SamTebbs33 wrote: > If you want to upgrade the whilewr intrinsics (which I think sounds OK to > me), then it will need auto-update code something like in > https://github.com/llvm/llvm-project/pull/120363/files#diff-0c0305d510a076cef711c006c1d9fd78c95cade1f597d21ee46fd753e6982316. > It might b

[clang] [llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

@@ -2033,6 +2041,25 @@ bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT, return false; } +bool AArch64TargetLowering::shouldExpandGetAliasLaneMask( SamTebbs33 wrote: It certainly can. Done. https://github.com/llvm/llvm-project/pull/1170

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