https://github.com/RKSimon commented:
Maybe add this to ReleaseNotes?
https://github.com/llvm/llvm-project/pull/93804
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RKSimon wrote:
@aniplcc if the x86 builtins handling is causing a problem - could we split
this so the generic c code intrinsics (andn, blsr etc.) are done first?
https://github.com/llvm/llvm-project/pull/94161
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@@ -614,12 +623,15 @@ _mm_shuffle_epi8(__m128i __a, __m128i __b)
///1: Clear the corresponding byte in the destination. \n
///0: Copy the selected source byte to the corresponding byte in the
///destination. \n
-///Bits [3:0] select the source byte to be
@@ -21,10 +21,29 @@ typedef int __v2si __attribute__((__vector_size__(8)));
typedef short __v4hi __attribute__((__vector_size__(8)));
typedef char __v8qi __attribute__((__vector_size__(8)));
RKSimon wrote:
Add a deprecation message if SSE2 is not defined or
RKSimon wrote:
> > So can we get all the mmx patches done in time for the 19.0 branch?
>
> Maybe? Depends on how the discussion on the other PR goes -- whether that
> proposal is acceptable, or if a different transition strategy is desired.
Apart from #96540 how many more patches do you
@@ -0,0 +1,248 @@
+//=== X86FixupBufferSecurityCheck.cpp Fix Buffer Security Check Call
RKSimon wrote:
Fix filename and '===// 'comment overflow
https://github.com/llvm/llvm-project/pull/95904
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@@ -48,6 +48,7 @@ set(sources
X86AvoidStoreForwardingBlocks.cpp
X86DynAllocaExpander.cpp
X86FixupSetCC.cpp
+ X86WinFixupBufferSecurityCheck.cpp
RKSimon wrote:
(style) alpha sorting
https://github.com/llvm/llvm-project/pull/95904
@@ -2296,33 +2296,55 @@ ExprResult
Sema::BuildBlockForLambdaConversion(SourceLocation CurrentLocation,
return BuildBlock;
}
+static FunctionDecl *getPatternFunctionDecl(FunctionDecl *FD) {
+ if (FD->getTemplatedKind() == FunctionDecl::TK_MemberSpecialization) {
+while
RKSimon wrote:
I'd prefer we rip off ALL the 3dnow/mmx bandaid in one big series of patches -
and not split across the 19.X/20.X releases.
So can we get all the mmx patches done in time for the 19.0 branch?
Also, this "might" have bigger impact than the KNL changes - should we announce
the
@@ -7,151 +7,16 @@
*===---===
*/
+// 3dNow intrinsics are no longer supported, and this header remains only as a
+// stub for users who were including it to get to _m_prefetch or
+// _m_prefetchw. Such uses
@@ -1825,32 +1818,32 @@ def : ProcModel;
-def : Proc<"k6-2", [FeatureX87, FeatureCX8, Feature3DNow],
+def : Proc<"k6-2", [FeatureX87, FeatureCX8],
RKSimon wrote:
These still need FeatureMMX and SSEPrefetch (or a similar flag)
RKSimon wrote:
@mahesh-attarde please can you rebase against trunk - I've cleaned up the test
checks to help with the codegen diff
https://github.com/llvm/llvm-project/pull/95904
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Author: Simon Pilgrim
Date: 2024-06-21T17:42:00+01:00
New Revision: 35bfbb3b21e9874d03b730e8ce4eb98b1dcd2d28
URL:
https://github.com/llvm/llvm-project/commit/35bfbb3b21e9874d03b730e8ce4eb98b1dcd2d28
DIFF:
https://github.com/llvm/llvm-project/commit/35bfbb3b21e9874d03b730e8ce4eb98b1dcd2d28.diff
@@ -1825,32 +1818,32 @@ def : ProcModel;
-def : Proc<"k6-2", [FeatureX87, FeatureCX8, Feature3DNow],
+def : Proc<"k6-2", [FeatureX87, FeatureCX8, FeatureMMX],
RKSimon wrote:
I think the best we can do is add FeaturePRFCHW as well?
@@ -0,0 +1,247 @@
+//=== X86FixupBufferSecurityCheck.cpp Fix Buffer Security Check
Call---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,247 @@
+//=== X86FixupBufferSecurityCheck.cpp Fix Buffer Security Check
Call---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,247 @@
+//=== X86FixupBufferSecurityCheck.cpp Fix Buffer Security Check
Call---===//
RKSimon wrote:
X86WinFixupBufferSecurityCheck.cpp
https://github.com/llvm/llvm-project/pull/95904
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https://github.com/RKSimon commented:
SGTM with a few minors
https://github.com/llvm/llvm-project/pull/95904
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https://github.com/RKSimon approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/95904
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RKSimon wrote:
> > How easy would it be to add an option for this to update inline asm? I'm
> > not asking you to do this here, I just want to know if this approach would
> > make it straightforward to add in the future.
>
> Should we touch the inline asm? (GCC doesn't
RKSimon wrote:
How easy would it be to add an option for this to update inline asm? I'm not
asking you to do this here, I just want to know if this approach would make it
straightforward to add in the future.
https://github.com/llvm/llvm-project/pull/96860
@@ -2834,7 +2834,7 @@ ABIArgInfo
X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned ,
unsigned ,
unsigned ) const {
- auto RT = Ty->getAs();
+ auto RT = Ty->castAs();
https://github.com/RKSimon updated
https://github.com/llvm/llvm-project/pull/96888
>From 7f6614d8df9a5ed2027f90d813695bc43f1044b2 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim
Date: Thu, 27 Jun 2024 11:09:32 +0100
Subject: [PATCH] [Sema] LambdaScopeForCallOperatorInstantiationRAII - fix typo
https://github.com/RKSimon closed
https://github.com/llvm/llvm-project/pull/96888
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RKSimon wrote:
Cheers - I'll push this (without the assert) in a moment - that shouldn't get
in the way of working out why they aren't always paired.
https://github.com/llvm/llvm-project/pull/96888
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Author: Simon Pilgrim
Date: 2024-06-19T16:55:33+01:00
New Revision: f7c96d5733915c4ea30dbd7852faffc9cef4aca9
URL:
https://github.com/llvm/llvm-project/commit/f7c96d5733915c4ea30dbd7852faffc9cef4aca9
DIFF:
https://github.com/llvm/llvm-project/commit/f7c96d5733915c4ea30dbd7852faffc9cef4aca9.diff
RKSimon wrote:
It would probably explain why the typo hasn't caused regression - I'm going off
static analysis reports here, not crash reports.
https://github.com/llvm/llvm-project/pull/96888
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Author: Simon Pilgrim
Date: 2024-06-27T13:09:48+01:00
New Revision: 4d167fb28b8c8b2e278fb09b1c435db6d6393d56
URL:
https://github.com/llvm/llvm-project/commit/4d167fb28b8c8b2e278fb09b1c435db6d6393d56
DIFF:
https://github.com/llvm/llvm-project/commit/4d167fb28b8c8b2e278fb09b1c435db6d6393d56.diff
https://github.com/RKSimon created
https://github.com/llvm/llvm-project/pull/96888
We should be checking for a failed dyn_cast on the ParentFD result - not the
loop invariant FD root value.
Seems to have been introduced in #65193
Noticed by static analyser (I have no specific test case).
@@ -9,95 +9,6 @@
@"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00"; [#uses=1]
define void @test(ptr %a) nounwind ssp {
-; MSVC-X86-LABEL: test:
RKSimon wrote:
where did the test checks go?
https://github.com/llvm/llvm-project/pull/95904
@@ -82,6 +94,8 @@ define void @tailcall_unrelated_frame() sspreq {
; LINUX-NEXT: .LBB1_2: # %CallStackCheckFailBlk
; LINUX-NEXT:.cfi_def_cfa_offset 16
; LINUX-NEXT:callq __stack_chk_fail@PLT
+
+
RKSimon wrote:
superfluous
@@ -114,250 +25,93 @@ return:; preds = %entry
declare void @escape(ptr)
define void @test_vla(i32 %n) nounwind ssp {
-; MSVC-X86-LABEL: test_vla:
-; MSVC-X86: # %bb.0:
-; MSVC-X86-NEXT:pushl %ebp
-; MSVC-X86-NEXT:movl %esp, %ebp
-; MSVC-X86-NEXT:pushl
Author: Simon Pilgrim
Date: 2024-06-27T12:29:55+01:00
New Revision: 286955caa32b5b9fd959176c85ffb925e8093a0d
URL:
https://github.com/llvm/llvm-project/commit/286955caa32b5b9fd959176c85ffb925e8093a0d
DIFF:
https://github.com/llvm/llvm-project/commit/286955caa32b5b9fd959176c85ffb925e8093a0d.diff
https://github.com/RKSimon approved this pull request.
LGTM - cheers
https://github.com/llvm/llvm-project/pull/96860
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@@ -159,6 +159,20 @@ AMDGPU Support
X86 Support
^^^
+- The MMX vector intrinsic functions from ``*mmintrin.h`` which
+ operate on `__m64` vectors, such as ``_mm_add_pi8``, have been
+ reimplemented to use the SSE2 instruction-set and XMM registers
+
@@ -49,12 +49,10 @@ typedef __bf16 __m128bh __attribute__((__vector_size__(16),
__aligned__(16)));
#endif
/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS
\
-
https://github.com/RKSimon edited
https://github.com/llvm/llvm-project/pull/96540
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https://github.com/RKSimon approved this pull request.
LGTM with a couple of minors
https://github.com/llvm/llvm-project/pull/96540
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@@ -159,6 +159,20 @@ AMDGPU Support
X86 Support
^^^
+- The MMX vector intrinsic functions from ``*mmintrin.h`` which
+ operate on `__m64` vectors, such as ``_mm_add_pi8``, have been
+ reimplemented to use the SSE2 instruction-set and XMM registers
+
@@ -43,6 +43,7 @@ typedef unsigned short __mmask16;
/* Rounding mode macros. */
#define _MM_FROUND_TO_NEAREST_INT 0x00
+#define _MM_FROUND_TIES_TO_EVEN 0x00
RKSimon wrote:
(very pedantic) but _MM_FROUND_TO_NEAREST_TIES_EVEN would more closely keep to
RKSimon wrote:
@aniplcc reverse ping
https://github.com/llvm/llvm-project/pull/94161
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https://github.com/RKSimon edited
https://github.com/llvm/llvm-project/pull/98505
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@@ -57594,6 +57599,86 @@ static SDValue combinePDEP(SDNode *N, SelectionDAG
,
return SDValue();
}
+// Fixup the MMX intrinsics' types: in IR they are expressed with <1 x i64>,
RKSimon wrote:
<1 x i64> makes more sense to me to avoid i64 legalization
https://github.com/RKSimon deleted
https://github.com/llvm/llvm-project/pull/98505
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RKSimon wrote:
GCC thread (for reference):
https://gcc.gnu.org/pipermail/gcc-patches/2024-July/657957.html
https://github.com/llvm/llvm-project/pull/99691
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https://github.com/RKSimon edited
https://github.com/llvm/llvm-project/pull/97721
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@@ -749,6 +749,11 @@ def TuningUseGLMDivSqrtCosts
: SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
"Use Goldmont specific floating point div/sqrt costs">;
+// Starting with Redwood Cove architecture, the branch has branch taken hint
+//
https://github.com/RKSimon closed
https://github.com/llvm/llvm-project/pull/95904
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@@ -171,14 +171,14 @@ constexpr FeatureBitset FeaturesClearwaterforest =
// Geode Processor.
constexpr FeatureBitset FeaturesGeode =
-FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
RKSimon wrote:
Do we need to add a
@@ -171,14 +171,14 @@ constexpr FeatureBitset FeaturesClearwaterforest =
// Geode Processor.
constexpr FeatureBitset FeaturesGeode =
-FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
RKSimon wrote:
I think we should add the
https://github.com/RKSimon edited
https://github.com/llvm/llvm-project/pull/96246
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https://github.com/RKSimon approved this pull request.
LGTM with a few minors
https://github.com/llvm/llvm-project/pull/96246
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@@ -481,7 +481,7 @@ defm WriteAESKeyGen : X86SchedWritePair;
// Key Generation.
// Carry-less multiplication instructions.
defm WriteCLMul : X86SchedWritePair;
-// EMMS/FEMMS
RKSimon wrote:
keep these - FEMMS still uses this sched class
@@ -936,6 +936,24 @@ X86 Support
^^^
- Remove knl/knm specific ISA supports: AVX512PF, AVX512ER, PREFETCHWT1
+- Support has been removed for the AMD "3DNow!" instruction-set.
+ Neither modern AMD CPUs, nor any Intel CPUs implement these
+ instructions, and they were
@@ -1301,7 +1301,7 @@ defm : Zn3WriteResXMMPair; // Key Gener
// Carry-less multiplication instructions.
defm : Zn3WriteResXMMPair;
-// EMMS/FEMMS
RKSimon wrote:
keep these - FEMMS still uses this sched class
https://github.com/llvm/llvm-project/pull/96246
@@ -7,7 +7,7 @@
define <2 x i32> @test_pswapdsi(<2 x i32> %a) nounwind readnone {
RKSimon wrote:
update test title
https://github.com/llvm/llvm-project/pull/96246
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@@ -1341,7 +1341,7 @@ defm : Zn4WriteResXMMPair; // Key Gener
// Carry-less multiplication instructions.
defm : Zn4WriteResXMMPair;
-// EMMS/FEMMS
RKSimon wrote:
keep these - FEMMS still uses this sched class
https://github.com/llvm/llvm-project/pull/96246
https://github.com/RKSimon approved this pull request.
LGTM - cheers
https://github.com/llvm/llvm-project/pull/99352
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