*RTL Design Engineer* (Modem design)
Location : Santa Clara Joining time : immediate Rate : Open for Full time or contract The Broad JD for the requirements is, · Verilog/VHDL RTL/Conformal Verification( LEC) · Working knowledge of Integrating multiple IPs and associated glue logic · Understanding of Power Management ( voltage domain, power domains, clock domains ) -- You received this message because you are subscribed to the Google Groups "Citrix and Sap problems" group. To unsubscribe from this group and stop receiving emails from it, send an email to citrix-and-sap-problems+unsubscr...@googlegroups.com. To post to this group, send email to citrix-and-sap-problems@googlegroups.com. Visit this group at https://groups.google.com/group/citrix-and-sap-problems. For more options, visit https://groups.google.com/d/optout.
