kasjer commented on code in PR #2919: URL: https://github.com/apache/mynewt-core/pull/2919#discussion_r1067124630
########## hw/bsp/nucleo-h723zg/bsp.yml: ########## @@ -0,0 +1,72 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +bsp.name: "NUCLEO-H723ZG" +bsp.url: https://www.st.com/en/evaluation-tools/nucleo-h723zg.html +bsp.maker: "STMicroelectronics" +bsp.arch: cortex_m7 +bsp.compiler: compiler/arm-none-eabi-m7 +bsp.linkerscript: + - "hw/bsp/nucleo-h723zg/nucleo-h723zg.ld" + - "@apache-mynewt-core/hw/mcu/stm/stm32h7xx/stm32h723.ld" +bsp.linkerscript.BOOT_LOADER.OVERWRITE: + - "hw/bsp/nucleo-h723zg/boot-nucleo-h723zg.ld" + - "@apache-mynewt-core/hw/mcu/stm/stm32h7xx/stm32h723.ld" +bsp.downloadscript: "hw/bsp/nucleo-h723zg/nucleo-h723zg_download.sh" +bsp.debugscript: "hw/bsp/nucleo-h723zg/nucleo-h723zg_debug.sh" +bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/nucleo-h723zg/nucleo-h723zg_download.cmd" +bsp.debugscript.WINDOWS.OVERWRITE: "hw/bsp/nucleo-h723zg/nucleo-h723zg_debug.cmd" Review Comment: Not needed anymore. .cmd files can be removed. ########## hw/bsp/nucleo-h723zg/src/hal_bsp.c: ########## @@ -0,0 +1,279 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "spiflash/spiflash.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32h723xx.h> +#include <stm32_common/stm32_hal.h> +#include <bus/drivers/spi_common.h> + +#if MYNEWT_VAL(ETH_0) +#include <stm32_eth/stm32_eth.h> +#include <stm32_eth/stm32_eth_cfg.h> +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM11, + .irq = TIM1_TRG_COM_TIM11_IRQn, +}; +#endif + +int dupa = 6; + +/* FIXME: this works but shouldn't it be dual bank? */ +const uint32_t stm32_flash_sectors[] = { + 0x08000000, /* 32kB */ + 0x08008000, /* 32kB */ + 0x08010000, /* 32kB */ + 0x08018000, /* 32kB */ + 0x08020000, /* 128kB */ + 0x08040000, /* 256kB */ + 0x08080000, /* 256kB */ + 0x080c0000, /* 256kB */ + 0x08100000, /* 256kB */ + 0x08140000, /* 256kB */ + 0x08180000, /* 256kB */ + 0x081c0000, /* 256kB */ Review Comment: This should have 8 sectors 128kB each ########## hw/bsp/nucleo-h723zg/src/hal_bsp.c: ########## @@ -0,0 +1,279 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "spiflash/spiflash.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32h723xx.h> +#include <stm32_common/stm32_hal.h> +#include <bus/drivers/spi_common.h> + +#if MYNEWT_VAL(ETH_0) +#include <stm32_eth/stm32_eth.h> +#include <stm32_eth/stm32_eth_cfg.h> +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM11, + .irq = TIM1_TRG_COM_TIM11_IRQn, +}; +#endif + +int dupa = 6; + +/* FIXME: this works but shouldn't it be dual bank? */ Review Comment: Comment dos not apply ########## hw/bsp/nucleo-h723zg/syscfg.yml: ########## @@ -0,0 +1,78 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + STM32_FLASH_SIZE_KB: + description: 'Total flash size in KB.' + value: 1024 + + STM32_FLASH_NUM_AREAS: + description: 'Number of flash sectors for a non-linear STM32 MCU.' + value: 12 Review Comment: should be 8 ########## hw/mcu/stm/stm32h7xx/include/mcu/stm32_hal.h: ########## @@ -0,0 +1,111 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef STM32_HAL_H +#define STM32_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <mcu/cortex_m7.h> + +#include "stm32h7xx_hal.h" +#include "stm32h7xx_hal_def.h" + +#include "stm32h7xx_mynewt_hal.h" + +/* hal_watchdog */ +#include "stm32h7xx_hal_iwdg.h" +#define STM32_HAL_WATCHDOG_CUSTOM_INIT(x) \ + do { \ + (x)->Init.Window = IWDG_WINDOW_DISABLE; \ + } while (0) + +/* hal_system_start */ +#define STM32_HAL_FLASH_REMAP() \ Review Comment: there is no point in line continuation ########## hw/mcu/stm/stm32_common/src/hal_uart.c: ########## @@ -134,12 +134,17 @@ static struct hal_uart_irq uart_irqs[3]; #if !MYNEWT_VAL(STM32_HAL_UART_HAS_SR) # define STATUS(x) ((x)->ISR) +#if !MYNEWT_VAL(MCU_STM32H7) Review Comment: I would switch condition not to have ! ```c #if MYNEWT_VAL(MCY_STM32H7) ``` It will be easier to read if more MCUs has this characteristics ########## hw/bsp/nucleo-h723zg/src/hal_bsp.c: ########## @@ -0,0 +1,279 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "spiflash/spiflash.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32h723xx.h> +#include <stm32_common/stm32_hal.h> +#include <bus/drivers/spi_common.h> + +#if MYNEWT_VAL(ETH_0) +#include <stm32_eth/stm32_eth.h> +#include <stm32_eth/stm32_eth_cfg.h> +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM11, + .irq = TIM1_TRG_COM_TIM11_IRQn, +}; +#endif + +int dupa = 6; + +/* FIXME: this works but shouldn't it be dual bank? */ +const uint32_t stm32_flash_sectors[] = { + 0x08000000, /* 32kB */ + 0x08008000, /* 32kB */ + 0x08010000, /* 32kB */ + 0x08018000, /* 32kB */ + 0x08020000, /* 128kB */ + 0x08040000, /* 256kB */ + 0x08080000, /* 256kB */ + 0x080c0000, /* 256kB */ + 0x08100000, /* 256kB */ + 0x08140000, /* 256kB */ + 0x08180000, /* 256kB */ + 0x081c0000, /* 256kB */ + 0x08200000, /* End of flash */ +}; + +#define SZ (sizeof(stm32_flash_sectors) / sizeof(stm32_flash_sectors[0])) +static_assert(MYNEWT_VAL(STM32_FLASH_NUM_AREAS) + 1 == SZ, + "STM32_FLASH_NUM_AREAS does not match flash sectors"); + +#if MYNEWT_VAL(UART_0) +const struct stm32_uart_cfg os_bsp_uart0_cfg = { + .suc_uart = USART3, + .suc_rcc_reg = &RCC->APB1LENR, + .suc_rcc_dev = RCC_APB1LENR_USART3EN, + .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART3, + .suc_irqn = USART3_IRQn, +}; +#endif + +#if MYNEWT_VAL(I2C_0) +/* + * The PB8 and PB9 pins are connected through jumpers in the board to + * both ADC_IN and I2C pins. To enable I2C functionality SB147/SB157 need + * to be removed (they are the default connections) and SB138/SB143 need + * to be shorted. + */ +const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = { + .hic_i2c = I2C1, + .hic_rcc_reg = &RCC->APB1ENR, Review Comment: APB1LENR ########## hw/bsp/nucleo-h723zg/src/hal_bsp.c: ########## @@ -0,0 +1,279 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "spiflash/spiflash.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32h723xx.h> +#include <stm32_common/stm32_hal.h> +#include <bus/drivers/spi_common.h> + +#if MYNEWT_VAL(ETH_0) +#include <stm32_eth/stm32_eth.h> +#include <stm32_eth/stm32_eth_cfg.h> +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM11, Review Comment: TIM11 not present TIM12 could be used instead ########## hw/bsp/nucleo-h723zg/src/hal_bsp.c: ########## @@ -0,0 +1,279 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "spiflash/spiflash.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32h723xx.h> +#include <stm32_common/stm32_hal.h> +#include <bus/drivers/spi_common.h> + +#if MYNEWT_VAL(ETH_0) +#include <stm32_eth/stm32_eth.h> +#include <stm32_eth/stm32_eth_cfg.h> +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM11, + .irq = TIM1_TRG_COM_TIM11_IRQn, +}; +#endif + +int dupa = 6; + +/* FIXME: this works but shouldn't it be dual bank? */ +const uint32_t stm32_flash_sectors[] = { + 0x08000000, /* 32kB */ + 0x08008000, /* 32kB */ + 0x08010000, /* 32kB */ + 0x08018000, /* 32kB */ + 0x08020000, /* 128kB */ + 0x08040000, /* 256kB */ + 0x08080000, /* 256kB */ + 0x080c0000, /* 256kB */ + 0x08100000, /* 256kB */ + 0x08140000, /* 256kB */ + 0x08180000, /* 256kB */ + 0x081c0000, /* 256kB */ + 0x08200000, /* End of flash */ +}; + +#define SZ (sizeof(stm32_flash_sectors) / sizeof(stm32_flash_sectors[0])) +static_assert(MYNEWT_VAL(STM32_FLASH_NUM_AREAS) + 1 == SZ, + "STM32_FLASH_NUM_AREAS does not match flash sectors"); + +#if MYNEWT_VAL(UART_0) +const struct stm32_uart_cfg os_bsp_uart0_cfg = { + .suc_uart = USART3, + .suc_rcc_reg = &RCC->APB1LENR, + .suc_rcc_dev = RCC_APB1LENR_USART3EN, + .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART3, + .suc_irqn = USART3_IRQn, +}; +#endif + +#if MYNEWT_VAL(I2C_0) +/* + * The PB8 and PB9 pins are connected through jumpers in the board to + * both ADC_IN and I2C pins. To enable I2C functionality SB147/SB157 need + * to be removed (they are the default connections) and SB138/SB143 need + * to be shorted. + */ +const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = { + .hic_i2c = I2C1, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C1EN, + .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C1, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_1) +const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = { + .hic_i2c = I2C2, + .hic_rcc_reg = &RCC->APB1ENR, Review Comment: APB1LENR ########## hw/mcu/stm/stm32h7xx/src/clock_stm32h7xx.c: ########## @@ -0,0 +1,279 @@ +/* + * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "stm32h7xx_hal_pwr_ex.h" +#include "stm32h7xx_hal.h" +#include <assert.h> + +/* + * This allows an user to have a custom clock configuration by zeroing + * every possible clock source in the syscfg. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) || MYNEWT_VAL(STM32_CLOCK_LSE) || \ + MYNEWT_VAL(STM32_CLOCK_HSI) || MYNEWT_VAL(STM32_CLOCK_LSI) + +/* + * HSI is turned on by default, but can be turned off and use HSE instead. + */ +#if (((MYNEWT_VAL(STM32_CLOCK_HSE) != 0) + (MYNEWT_VAL(STM32_CLOCK_HSI) != 0)) < 1) +#error "At least one of HSE or HSI clock source must be enabled" +#endif + +void +SystemClock_Config(void) +{ + RCC_OscInitTypeDef osc_init = {0}; + RCC_ClkInitTypeDef clk_init = {0}; + HAL_StatusTypeDef status; + + + /* Enable the MCU instruction cache */ +#if MYNEWT_VAL(STM32_ENABLE_ICACHE) + SCB_EnableICache(); +#endif + + /* + * Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /* + * The voltage scaling allows optimizing the power consumption when the + * device is clocked below the maximum system frequency, to update the + * voltage scaling value regarding system frequency refer to product + * datasheet. + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(MYNEWT_VAL(STM32_CLOCK_VOLTAGESCALING_CONFIG)); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE; + + /* + * LSI is used to clock the independent watchdog and optionally the RTC. + * It can be disabled per user request, but is automatically enabled again + * when the IWDG is started. + * + * XXX currently the watchdog is not optional, so there's no point in + * disabling LSI through syscfg. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSI; +#if MYNEWT_VAL(STM32_CLOCK_LSI) + osc_init.LSIState = RCC_LSI_ON; +#else + osc_init.LSIState = RCC_LSI_OFF; +#endif + + /* + * LSE is only used to clock the RTC. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSE; +#if (MYNEWT_VAL(STM32_CLOCK_LSE) == 0) + osc_init.LSEState = RCC_LSE_OFF; +#elif MYNEWT_VAL(STM32_CLOCK_LSE_BYPASS) + osc_init.LSEState = RCC_LSE_BYPASS; +#else + osc_init.LSEState = RCC_LSE_ON; +#endif + + /* + * HSE Oscillator (can be used as PLL, SYSCLK and RTC clock source) + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE; +#if MYNEWT_VAL(STM32_CLOCK_HSE_BYPASS) + osc_init.HSEState = RCC_HSE_BYPASS; +#else + osc_init.HSEState = RCC_HSE_ON; +#endif +#endif + + /* + * HSI Oscillator (can be used as PLL and SYSCLK clock source). It is + * already turned on by default but a new calibration setting might be + * used. If the user chooses to turn it off, it must be turned off after + * SYSCLK was updated to use HSE/PLL. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSI) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI; + osc_init.HSIState = RCC_HSI_ON; + /* HSI calibration is not optional when HSI is enabled */ + osc_init.HSICalibrationValue = MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION); + +#if MYNEWT_VAL(STM32_CLOCK_HSI) && \ + !IS_RCC_HSICALIBRATION_VALUE(MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION)) +#error "Invalid HSI calibration value" +#endif +#endif + + /* + * Default to HSE as source, when both HSE and HSI are enabled. + * + * TODO: option to let the PLL turned off could be added, because + * both HSI and HSE can be used as SYSCLK source. + */ + osc_init.PLL.PLLState = RCC_PLL_ON; +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE; +#else + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSI; +#endif + +#if !IS_RCC_PLLM_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLM)) +#error "PLLM value is invalid" +#endif + +#if !IS_RCC_PLLN_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLN)) +#error "PLLN value is invalid" +#endif + +/* + * Redefine this macro for F7, because the Cube HAL is using typecast which + * is not valid when trying to catch errors at build time. + */ +#if MYNEWT_VAL(MCU_STM32F7) +#undef IS_RCC_PLLP_VALUE +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || \ + ((VALUE) == 6U) || ((VALUE) == 8U)) +#endif + +#if !IS_RCC_PLLP_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLP)) +#error "PLLP value is invalid" +#endif + +#if !IS_RCC_PLLQ_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ)) +#error "PLLQ value is invalid" +#endif + + osc_init.PLL.PLLM = MYNEWT_VAL(STM32_CLOCK_PLL_PLLM); + osc_init.PLL.PLLN = MYNEWT_VAL(STM32_CLOCK_PLL_PLLN); + osc_init.PLL.PLLP = MYNEWT_VAL(STM32_CLOCK_PLL_PLLP); + osc_init.PLL.PLLQ = MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ); + +#if MYNEWT_VAL(STM32_CLOCK_PLL_PLLR) + +#if !IS_RCC_PLLR_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLR)) +#error "PLLR value is invalid" +#endif + + osc_init.PLL.PLLR = MYNEWT_VAL(STM32_CLOCK_PLL_PLLR); + osc_init.PLL.PLLRGE = MYNEWT_VAL(STM32_CLOCK_PLL_PLLR); +#endif /* MYNEWT_VAL(STM32_CLOCK_PLL_PLLR) */ + + status = HAL_RCC_OscConfig(&osc_init); + if (status != HAL_OK) { + assert(0); + } + +#if MYNEWT_VAL(STM32_CLOCK_ENABLE_OVERDRIVE) + /* + * Activate the Over-Drive mode + */ + status = HAL_PWREx_EnableOverDrive(); + if (status != HAL_OK) { + assert(0); + } +#endif + + /* + * Select PLL as system clock source and configure the HCLK, PCLK1 and + * PCLK2 clocks dividers. HSI and HSE are also valid system clock sources, + * although there is no much point in supporting them now. + */ + clk_init.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + +#if !IS_RCC_HCLK(MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER)) +#error "AHB clock divider is invalid" +#endif + +#if !IS_RCC_PCLK1(MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER)) +#error "APB1 clock divider is invalid" +#endif + +#if !IS_RCC_PCLK1(MYNEWT_VAL(STM32_CLOCK_APB2_DIVIDER)) +#error "APB2 clock divider is invalid" +#endif + + clk_init.AHBCLKDivider = MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER); + clk_init.APB1CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER); + clk_init.APB2CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB2_DIVIDER); + clk_init.APB3CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB3_DIVIDER); + clk_init.APB4CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB4_DIVIDER); + +#if !IS_FLASH_LATENCY(MYNEWT_VAL(STM32_FLASH_LATENCY)) +#error "Flash latency value is invalid" +#endif + + status = HAL_RCC_ClockConfig(&clk_init, MYNEWT_VAL(STM32_FLASH_LATENCY)); + if (status != HAL_OK) { + assert(0); + } + +#if ((MYNEWT_VAL(STM32_CLOCK_HSI) == 0) || (MYNEWT_VAL(STM32_CLOCK_HSE) == 0)) + /* + * Turn off HSE/HSI oscillator; this must be done at the end because + * SYSCLK source has to be updated first. + */ + osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE; +#if (MYNEWT_VAL(STM32_CLOCK_HSE) == 0) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE; + osc_init.HSEState = RCC_HSE_OFF; +#endif +#if (MYNEWT_VAL(STM32_CLOCK_HSI) == 0) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI; + osc_init.HSIState = RCC_HSI_OFF; +#endif + osc_init.PLL.PLLState = RCC_PLL_NONE; + + status = HAL_RCC_OscConfig(&osc_init); + if (status != HAL_OK) { + assert(0); + } +#endif + +#if ART_ACCLERATOR_ENABLE + __HAL_FLASH_ART_ENABLE(); +#endif + +#if PREFETCH_ENABLE + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif + + /* + * These are flash instruction and data caches, not the be confused with + * MCU caches. + */ +#if INSTRUCTION_CACHE_ENABLE + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); +#endif + +#if DATA_CACHE_ENABLE + __HAL_FLASH_DATA_CACHE_ENABLE(); +#endif Review Comment: Macros don't apply to H7 ########## hw/bsp/nucleo-h723zg/boot-nucleo-h723zg.ld: ########## @@ -0,0 +1,30 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 64K + DTCM (rwx) : ORIGIN = 0x24000000, LENGTH = 128K + RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 32K Review Comment: ``` ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Bootloader area */ RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 320K /* AXI (128) + AXI/ITCM (192) */ RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 32K /* SRAM1 + SRMA2 */ RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 16K /* SRAM4 */ ``` ########## hw/mcu/stm/stm32h7xx/src/hal_reset_cause.c: ########## @@ -0,0 +1,47 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <hal/hal_system.h> + +#include "stm32h7xx_hal_def.h" + +enum hal_reset_reason +hal_reset_cause(void) +{ + static enum hal_reset_reason reason; + uint32_t reg; + + if (reason) { + return reason; + } + + reg = RCC->CSR; + if (reg & RCC_RSR_WWDG1RSTF || reg & RCC_RSR_IWDG1RSTF) { + reason = HAL_RESET_WATCHDOG; + } else if (reg & RCC_RSR_SFTRSTF) { + reason = HAL_RESET_SOFT; + } else if (reg & RCC_RSR_PINRSTF) { + reason = HAL_RESET_PIN; + } else if (reg & RCC_RSR_BORRSTF) { + reason = HAL_RESET_BROWNOUT; + } else { + reason = HAL_RESET_POR; + } + RCC->CSR |= RCC_RSR_RMVF; Review Comment: This should be RCC->RSR ########## hw/mcu/stm/stm32h7xx/src/hal_reset_cause.c: ########## @@ -0,0 +1,47 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <hal/hal_system.h> + +#include "stm32h7xx_hal_def.h" + +enum hal_reset_reason +hal_reset_cause(void) +{ + static enum hal_reset_reason reason; + uint32_t reg; + + if (reason) { + return reason; + } + + reg = RCC->CSR; Review Comment: This should be RCC->RSR ########## hw/bsp/nucleo-h723zg/src/hal_bsp.c: ########## @@ -0,0 +1,279 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "spiflash/spiflash.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32h723xx.h> +#include <stm32_common/stm32_hal.h> +#include <bus/drivers/spi_common.h> + +#if MYNEWT_VAL(ETH_0) +#include <stm32_eth/stm32_eth.h> +#include <stm32_eth/stm32_eth_cfg.h> +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM11, + .irq = TIM1_TRG_COM_TIM11_IRQn, +}; +#endif + +int dupa = 6; + +/* FIXME: this works but shouldn't it be dual bank? */ +const uint32_t stm32_flash_sectors[] = { + 0x08000000, /* 32kB */ + 0x08008000, /* 32kB */ + 0x08010000, /* 32kB */ + 0x08018000, /* 32kB */ + 0x08020000, /* 128kB */ + 0x08040000, /* 256kB */ + 0x08080000, /* 256kB */ + 0x080c0000, /* 256kB */ + 0x08100000, /* 256kB */ + 0x08140000, /* 256kB */ + 0x08180000, /* 256kB */ + 0x081c0000, /* 256kB */ + 0x08200000, /* End of flash */ +}; + +#define SZ (sizeof(stm32_flash_sectors) / sizeof(stm32_flash_sectors[0])) +static_assert(MYNEWT_VAL(STM32_FLASH_NUM_AREAS) + 1 == SZ, + "STM32_FLASH_NUM_AREAS does not match flash sectors"); + +#if MYNEWT_VAL(UART_0) +const struct stm32_uart_cfg os_bsp_uart0_cfg = { + .suc_uart = USART3, + .suc_rcc_reg = &RCC->APB1LENR, + .suc_rcc_dev = RCC_APB1LENR_USART3EN, + .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART3, + .suc_irqn = USART3_IRQn, +}; +#endif + +#if MYNEWT_VAL(I2C_0) +/* + * The PB8 and PB9 pins are connected through jumpers in the board to + * both ADC_IN and I2C pins. To enable I2C functionality SB147/SB157 need + * to be removed (they are the default connections) and SB138/SB143 need + * to be shorted. + */ +const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = { + .hic_i2c = I2C1, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C1EN, + .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C1, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_1) +const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = { + .hic_i2c = I2C2, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C2EN, + .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C2, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_2) +const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = { + .hic_i2c = I2C3, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C3EN, + .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C3, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_3) +const struct stm32_hal_i2c_cfg os_bsp_i2c3_cfg = { + .hic_i2c = I2C4, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C4EN, + .hic_pin_sda = MYNEWT_VAL(I2C_3_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_3_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C4, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(ETH_0) +const struct stm32_eth_cfg os_bsp_eth0_cfg = { + /* + * PORTA + * PA1 - ETH_RMII_REF_CLK + * PA2 - ETH_RMII_MDIO + * PA7 - ETH_RMII_CRS_DV + */ + .sec_port_mask[0] = (1 << 1) | (1 << 2) | (1 << 7), + + /* + * PORTB + * PB13 - ETH_RMII_TXD1 + */ + .sec_port_mask[1] = (1 << 13), + + /* + * PORTC + * PC1 - ETH_RMII_MDC + * PC4 - ETH_RMII_RXD0 + * PC5 - ETH_RMII_RXD1 + */ + .sec_port_mask[2] = (1 << 1) | (1 << 4) | (1 << 5), + + /* + * PORTG + * PG11 - ETH_RMII_TXEN + * PG13 - ETH_RMII_TXD0 + */ + .sec_port_mask[6] = (1 << 11) | (1 << 13), + .sec_phy_type = LAN_8742_RMII, + .sec_phy_irq = -1 +}; +#endif + +/* FIXME */ +static const struct hal_bsp_mem_dump dump_cfg[] = { + [0] = { + .hbmd_start = &_ram_start, + .hbmd_size = RAM_SIZE, + }, + [1] = { + .hbmd_start = &_dtcmram_start, + .hbmd_size = DTCMRAM_SIZE, + }, + [2] = { + .hbmd_start = &_itcmram_start, Review Comment: linker script does not provide this symbol yet ########## hw/mcu/stm/stm32h7xx/include/mcu/cortex_m7.h: ########## @@ -0,0 +1,39 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_CORTEX_M4_H__ +#define __MCU_CORTEX_M4_H__ Review Comment: Cortex-M7 ########## hw/mcu/stm/stm32h7xx/src/hal_timer_freq.c: ########## @@ -0,0 +1,135 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "os/mynewt.h" + +#include <assert.h> +#include <inttypes.h> +#include "stm32h7xx_hal_rcc.h" + +static uint32_t +stm32_hal_timer_abp_clk_div(uint32_t divider) +{ + switch (divider) { + case RCC_HCLK_DIV1: + return 1; + case RCC_HCLK_DIV2: + return 2; + case RCC_HCLK_DIV4: + return 4; + case RCC_HCLK_DIV8: + return 8; + case RCC_HCLK_DIV16: + return 16; + } + return 0; +} + +uint32_t +stm32_hal_timer_get_freq(void *timx) +{ + uintptr_t regs = (uintptr_t)timx; + RCC_ClkInitTypeDef clocks; + uint32_t flashLatency; + uint32_t freq = 0; + uint32_t div = 0; + + HAL_RCC_GetClockConfig(&clocks, &flashLatency); + + switch (regs) { +#ifdef TIM1 + case (uintptr_t)TIM1: +#endif +#ifdef TIM8 + case (uintptr_t)TIM8: +#endif +#ifdef TIM9 + case (uintptr_t)TIM9: +#endif +#ifdef TIM10 + case (uintptr_t)TIM10: +#endif +#ifdef TIM11 + case (uintptr_t)TIM11: +#endif Review Comment: TIM9, TIM10, TIM11, TIM20 are not present in any H7 chip so far ########## hw/mcu/stm/stm32h7xx/src/clock_stm32h7xx.c: ########## @@ -0,0 +1,279 @@ +/* + * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "stm32h7xx_hal_pwr_ex.h" +#include "stm32h7xx_hal.h" +#include <assert.h> + +/* + * This allows an user to have a custom clock configuration by zeroing + * every possible clock source in the syscfg. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) || MYNEWT_VAL(STM32_CLOCK_LSE) || \ + MYNEWT_VAL(STM32_CLOCK_HSI) || MYNEWT_VAL(STM32_CLOCK_LSI) + +/* + * HSI is turned on by default, but can be turned off and use HSE instead. + */ +#if (((MYNEWT_VAL(STM32_CLOCK_HSE) != 0) + (MYNEWT_VAL(STM32_CLOCK_HSI) != 0)) < 1) +#error "At least one of HSE or HSI clock source must be enabled" +#endif + +void +SystemClock_Config(void) +{ + RCC_OscInitTypeDef osc_init = {0}; + RCC_ClkInitTypeDef clk_init = {0}; + HAL_StatusTypeDef status; + + + /* Enable the MCU instruction cache */ +#if MYNEWT_VAL(STM32_ENABLE_ICACHE) + SCB_EnableICache(); +#endif + + /* + * Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /* + * The voltage scaling allows optimizing the power consumption when the + * device is clocked below the maximum system frequency, to update the + * voltage scaling value regarding system frequency refer to product + * datasheet. + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(MYNEWT_VAL(STM32_CLOCK_VOLTAGESCALING_CONFIG)); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE; + + /* + * LSI is used to clock the independent watchdog and optionally the RTC. + * It can be disabled per user request, but is automatically enabled again + * when the IWDG is started. + * + * XXX currently the watchdog is not optional, so there's no point in + * disabling LSI through syscfg. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSI; +#if MYNEWT_VAL(STM32_CLOCK_LSI) + osc_init.LSIState = RCC_LSI_ON; +#else + osc_init.LSIState = RCC_LSI_OFF; +#endif + + /* + * LSE is only used to clock the RTC. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSE; +#if (MYNEWT_VAL(STM32_CLOCK_LSE) == 0) + osc_init.LSEState = RCC_LSE_OFF; +#elif MYNEWT_VAL(STM32_CLOCK_LSE_BYPASS) + osc_init.LSEState = RCC_LSE_BYPASS; +#else + osc_init.LSEState = RCC_LSE_ON; +#endif + + /* + * HSE Oscillator (can be used as PLL, SYSCLK and RTC clock source) + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE; +#if MYNEWT_VAL(STM32_CLOCK_HSE_BYPASS) + osc_init.HSEState = RCC_HSE_BYPASS; +#else + osc_init.HSEState = RCC_HSE_ON; +#endif +#endif + + /* + * HSI Oscillator (can be used as PLL and SYSCLK clock source). It is + * already turned on by default but a new calibration setting might be + * used. If the user chooses to turn it off, it must be turned off after + * SYSCLK was updated to use HSE/PLL. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSI) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI; + osc_init.HSIState = RCC_HSI_ON; + /* HSI calibration is not optional when HSI is enabled */ + osc_init.HSICalibrationValue = MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION); + +#if MYNEWT_VAL(STM32_CLOCK_HSI) && \ + !IS_RCC_HSICALIBRATION_VALUE(MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION)) +#error "Invalid HSI calibration value" +#endif +#endif + + /* + * Default to HSE as source, when both HSE and HSI are enabled. + * + * TODO: option to let the PLL turned off could be added, because + * both HSI and HSE can be used as SYSCLK source. + */ + osc_init.PLL.PLLState = RCC_PLL_ON; +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE; +#else + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSI; +#endif + +#if !IS_RCC_PLLM_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLM)) +#error "PLLM value is invalid" +#endif + +#if !IS_RCC_PLLN_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLN)) +#error "PLLN value is invalid" +#endif + +/* + * Redefine this macro for F7, because the Cube HAL is using typecast which + * is not valid when trying to catch errors at build time. + */ +#if MYNEWT_VAL(MCU_STM32F7) +#undef IS_RCC_PLLP_VALUE +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || \ + ((VALUE) == 6U) || ((VALUE) == 8U)) +#endif + +#if !IS_RCC_PLLP_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLP)) +#error "PLLP value is invalid" +#endif + +#if !IS_RCC_PLLQ_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ)) +#error "PLLQ value is invalid" +#endif + + osc_init.PLL.PLLM = MYNEWT_VAL(STM32_CLOCK_PLL_PLLM); + osc_init.PLL.PLLN = MYNEWT_VAL(STM32_CLOCK_PLL_PLLN); + osc_init.PLL.PLLP = MYNEWT_VAL(STM32_CLOCK_PLL_PLLP); + osc_init.PLL.PLLQ = MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ); + +#if MYNEWT_VAL(STM32_CLOCK_PLL_PLLR) Review Comment: PLL_PLLR is not optional and should be handled like PLLM/N/P/Q ########## hw/mcu/stm/stm32h7xx/src/hal_timer_freq.c: ########## @@ -0,0 +1,135 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "os/mynewt.h" + +#include <assert.h> +#include <inttypes.h> +#include "stm32h7xx_hal_rcc.h" + +static uint32_t +stm32_hal_timer_abp_clk_div(uint32_t divider) +{ + switch (divider) { + case RCC_HCLK_DIV1: + return 1; + case RCC_HCLK_DIV2: + return 2; + case RCC_HCLK_DIV4: + return 4; + case RCC_HCLK_DIV8: + return 8; + case RCC_HCLK_DIV16: + return 16; + } + return 0; +} + +uint32_t +stm32_hal_timer_get_freq(void *timx) +{ + uintptr_t regs = (uintptr_t)timx; + RCC_ClkInitTypeDef clocks; + uint32_t flashLatency; + uint32_t freq = 0; + uint32_t div = 0; + + HAL_RCC_GetClockConfig(&clocks, &flashLatency); + + switch (regs) { +#ifdef TIM1 + case (uintptr_t)TIM1: +#endif +#ifdef TIM8 + case (uintptr_t)TIM8: +#endif +#ifdef TIM9 + case (uintptr_t)TIM9: +#endif +#ifdef TIM10 + case (uintptr_t)TIM10: +#endif +#ifdef TIM11 + case (uintptr_t)TIM11: +#endif +#ifdef TIM15 + case (uintptr_t)TIM15: +#endif +#ifdef TIM16 + case (uintptr_t)TIM16: +#endif +#ifdef TIM17 + case (uintptr_t)TIM17: +#endif +#ifdef TIM20 + case (uintptr_t)TIM20: +#endif + freq = HAL_RCC_GetPCLK2Freq(); + div = stm32_hal_timer_abp_clk_div(clocks.APB2CLKDivider); + break; + +#ifdef TIM2 + case (uintptr_t)TIM2: +#endif +#ifdef TIM3 + case (uintptr_t)TIM3: +#endif +#ifdef TIM4 + case (uintptr_t)TIM4: +#endif +#ifdef TIM5 + case (uintptr_t)TIM5: +#endif +#ifdef TIM6 + case (uintptr_t)TIM6: +#endif +#ifdef TIM7 + case (uintptr_t)TIM7: +#endif + +#ifdef TIM12 + case (uintptr_t)TIM12: +#endif +#ifdef TIM13 + case (uintptr_t)TIM13: +#endif +#ifdef TIM14 + case (uintptr_t)TIM14: +#endif + freq = HAL_RCC_GetPCLK1Freq(); + div = stm32_hal_timer_abp_clk_div(clocks.APB1CLKDivider); + break; Review Comment: TIM23 and TIM24 could also be put here ########## hw/bus/drivers/spi_stm32/src/spi_stm32.c: ########## @@ -613,7 +613,11 @@ spi_stm32_configure(struct bus_dev *bdev, struct bus_node *bnode) if (prescaler > 7) { rc = SYS_EINVAL; } else { +#if !MYNEWT_VAL(MCU_STM32H7) Review Comment: Could you please revers condition as not to have ! ? ########## hw/mcu/stm/stm32_common/src/hal_spi.c: ########## @@ -286,10 +286,15 @@ spi_ss_isr(void *arg) /* * Chip select done. Check whether there's pending data to RX. */ +#if !MYNEWT_VAL(MCU_STM32H7) Review Comment: I would remove ! from condition and swap code blocks for future readability ########## hw/bsp/nucleo-h723zg/syscfg.yml: ########## @@ -0,0 +1,78 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + STM32_FLASH_SIZE_KB: + description: 'Total flash size in KB.' + value: 1024 + + STM32_FLASH_NUM_AREAS: + description: 'Number of flash sectors for a non-linear STM32 MCU.' + value: 12 + + BSP_FLASH_SPI_BUS: + description: 'bus name SPIFLASH is connected to' + value: '"spi0"' + + BSP_FLASH_SPI_NAME: + description: 'SPIFLASH device name' + value: '"spiflash0"' + +syscfg.vals: + REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG + CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS + NFFS_FLASH_AREA: FLASH_AREA_NFFS + COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1 + STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE0' + STM32_CLOCK_HSI: 1 + STM32_CLOCK_HSE: 0 + STM32_CLOCK_HSE_BYPASS: 0 + STM32_CLOCK_PLL_PLLM: 4 + STM32_CLOCK_PLL_PLLN: 34 + STM32_CLOCK_PLL_PLLP: 1 + STM32_CLOCK_PLL_PLLQ: 4 + STM32_CLOCK_PLL_PLLR: 2 + STM32_CLOCK_ENABLE_OVERDRIVE: 0 + STM32_CLOCK_AHB_DIVIDER: 'RCC_HCLK_DIV2' + STM32_CLOCK_APB1_DIVIDER: 'RCC_APB1_DIV4' + STM32_CLOCK_APB2_DIVIDER: 'RCC_APB1_DIV2' + STM32_CLOCK_APB3_DIVIDER: 'RCC_APB3_DIV2' + STM32_CLOCK_APB4_DIVIDER: 'RCC_APB4_DIV2' + STM32_CLOCK_PLLRGE: 'RCC_PLL1VCIRANGE_3' + STM32_FLASH_LATENCY: 'FLASH_LATENCY_3' + STM32_FLASH_PREFETCH_ENABLE: 1 + STM32_ART_ACCLERATOR_ENABLE: 1 + STM32_ENABLE_ICACHE: 0 + UART_0_PIN_TX: 'MCU_GPIO_PORTD(8)' + UART_0_PIN_RX: 'MCU_GPIO_PORTD(9)' + SPI_0_PIN_SS: 'MCU_GPIO_PORTD(14)' + SPI_0_PIN_SCK: 'MCU_GPIO_PORTA(5)' + SPI_0_PIN_MISO: 'MCU_GPIO_PORTA(6)' + SPI_0_PIN_MOSI: 'MCU_GPIO_PORTB(5)' + I2C_0_PIN_SCL: 'MCU_GPIO_PORTB(8)' + I2C_0_PIN_SDA: 'MCU_GPIO_PORTB(9)' + I2C_1_PIN_SCL: 'MCU_GPIO_PORTF(1)' + I2C_1_PIN_SDA: 'MCU_GPIO_PORTF(0)' + I2C_2_PIN_SCL: 'MCU_GPIO_PORTA(8)' + I2C_2_PIN_SDA: 'MCU_GPIO_PORTC(9)' + I2C_3_PIN_SCL: 'MCU_GPIO_PORTD(12)' + I2C_3_PIN_SDA: 'MCU_GPIO_PORTD(13)' + TIMER_0_TIM: 'TIM12' + TIMER_1_TIM: 'TIM10' + TIMER_2_TIM: 'TIM11' Review Comment: TIM10 TIM11 are not present on H7 TIM13, TIM14 could be used instead ########## hw/bsp/nucleo-h723zg/syscfg.yml: ########## @@ -0,0 +1,78 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + STM32_FLASH_SIZE_KB: + description: 'Total flash size in KB.' + value: 1024 + + STM32_FLASH_NUM_AREAS: + description: 'Number of flash sectors for a non-linear STM32 MCU.' + value: 12 + + BSP_FLASH_SPI_BUS: + description: 'bus name SPIFLASH is connected to' + value: '"spi0"' + + BSP_FLASH_SPI_NAME: + description: 'SPIFLASH device name' + value: '"spiflash0"' + +syscfg.vals: + REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG + CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS + NFFS_FLASH_AREA: FLASH_AREA_NFFS + COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1 + STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE0' + STM32_CLOCK_HSI: 1 + STM32_CLOCK_HSE: 0 + STM32_CLOCK_HSE_BYPASS: 0 + STM32_CLOCK_PLL_PLLM: 4 + STM32_CLOCK_PLL_PLLN: 34 + STM32_CLOCK_PLL_PLLP: 1 + STM32_CLOCK_PLL_PLLQ: 4 + STM32_CLOCK_PLL_PLLR: 2 + STM32_CLOCK_ENABLE_OVERDRIVE: 0 + STM32_CLOCK_AHB_DIVIDER: 'RCC_HCLK_DIV2' + STM32_CLOCK_APB1_DIVIDER: 'RCC_APB1_DIV4' + STM32_CLOCK_APB2_DIVIDER: 'RCC_APB1_DIV2' + STM32_CLOCK_APB3_DIVIDER: 'RCC_APB3_DIV2' + STM32_CLOCK_APB4_DIVIDER: 'RCC_APB4_DIV2' + STM32_CLOCK_PLLRGE: 'RCC_PLL1VCIRANGE_3' + STM32_FLASH_LATENCY: 'FLASH_LATENCY_3' + STM32_FLASH_PREFETCH_ENABLE: 1 + STM32_ART_ACCLERATOR_ENABLE: 1 Review Comment: STM32_FLASH_PREFETCH_ENABLE and STM32_ART_ACCLERATOR_ENABLE are not applicable ########## hw/mcu/stm/stm32h7xx/stm32h723.ld: ########## @@ -0,0 +1,214 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __coredata_start__ + * __coredata_end__ + * __corebss_start__ + * __corebss_end__ + * __ecoredata + * __ecorebss + */ +ENTRY(Reset_Handler) + +_estack = ORIGIN(DTCM) + LENGTH(DTCM); + +SECTIONS +{ + /* Reserve space at the start of the image for the header. */ + .imghdr (NOLOAD): + { + . = . + _imghdr_size; + } > FLASH + + __text = .; + + .text : + { + __isr_vector_start = .; + KEEP(*(.isr_vector)) + __isr_vector_end = .; + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + + __exidx_end = .; + + __etext = .; + + .vector_relocation : + { + . = ALIGN(4); + __vector_tbl_reloc__ = .; + . = . + (__isr_vector_end - __isr_vector_start); + . = ALIGN(4); + } > DTCM + + .coredata : + { + __coredata_start__ = .; + *(.data.core) + . = ALIGN(4); + __coredata_end__ = .; + } > DTCM AT > FLASH + + __ecoredata = __etext + SIZEOF(.coredata); + + _sidata = LOADADDR(.data); + + .data : + { + . = ALIGN(4); + _sdata = .; + __data_start__ = _sdata; + *(vtable) + *(.data*) + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + _edata = .; + __data_end__ = _edata; + + } > DTCM AT > FLASH + + .corebss (NOLOAD): + { + . = ALIGN(4); + __corebss_start__ = .; + *(.bss.core) + . = ALIGN(4); + __corebss_end__ = .; + *(.corebss*) + *(.bss.core.nz) + . = ALIGN(4); + __ecorebss = .; + } > DTCM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } > DTCM + + . = ALIGN(8); + __HeapBase = .; + __HeapLimit = ORIGIN(DTCM) + LENGTH(DTCM); + + _ram_start = ORIGIN(DTCM); + _dtcmram_start = ORIGIN(DTCM); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > DTCM + + /* Set stack top to end of DTCM; stack limit is bottom of stack */ + __StackTop = ORIGIN(DTCM) + LENGTH(DTCM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); Review Comment: This is just reminder in case RAM is switched from DTCM to AXI some of those may need change as well ########## hw/mcu/stm/stm32h7xx/src/clock_stm32h7xx.c: ########## @@ -0,0 +1,279 @@ +/* + * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "stm32h7xx_hal_pwr_ex.h" +#include "stm32h7xx_hal.h" +#include <assert.h> + +/* + * This allows an user to have a custom clock configuration by zeroing + * every possible clock source in the syscfg. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) || MYNEWT_VAL(STM32_CLOCK_LSE) || \ + MYNEWT_VAL(STM32_CLOCK_HSI) || MYNEWT_VAL(STM32_CLOCK_LSI) + +/* + * HSI is turned on by default, but can be turned off and use HSE instead. + */ +#if (((MYNEWT_VAL(STM32_CLOCK_HSE) != 0) + (MYNEWT_VAL(STM32_CLOCK_HSI) != 0)) < 1) +#error "At least one of HSE or HSI clock source must be enabled" +#endif + +void +SystemClock_Config(void) +{ + RCC_OscInitTypeDef osc_init = {0}; + RCC_ClkInitTypeDef clk_init = {0}; + HAL_StatusTypeDef status; + + + /* Enable the MCU instruction cache */ +#if MYNEWT_VAL(STM32_ENABLE_ICACHE) + SCB_EnableICache(); +#endif + + /* + * Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /* + * The voltage scaling allows optimizing the power consumption when the + * device is clocked below the maximum system frequency, to update the + * voltage scaling value regarding system frequency refer to product + * datasheet. + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(MYNEWT_VAL(STM32_CLOCK_VOLTAGESCALING_CONFIG)); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE; + + /* + * LSI is used to clock the independent watchdog and optionally the RTC. + * It can be disabled per user request, but is automatically enabled again + * when the IWDG is started. + * + * XXX currently the watchdog is not optional, so there's no point in + * disabling LSI through syscfg. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSI; +#if MYNEWT_VAL(STM32_CLOCK_LSI) + osc_init.LSIState = RCC_LSI_ON; +#else + osc_init.LSIState = RCC_LSI_OFF; +#endif + + /* + * LSE is only used to clock the RTC. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSE; +#if (MYNEWT_VAL(STM32_CLOCK_LSE) == 0) + osc_init.LSEState = RCC_LSE_OFF; +#elif MYNEWT_VAL(STM32_CLOCK_LSE_BYPASS) + osc_init.LSEState = RCC_LSE_BYPASS; +#else + osc_init.LSEState = RCC_LSE_ON; +#endif + + /* + * HSE Oscillator (can be used as PLL, SYSCLK and RTC clock source) + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE; +#if MYNEWT_VAL(STM32_CLOCK_HSE_BYPASS) + osc_init.HSEState = RCC_HSE_BYPASS; +#else + osc_init.HSEState = RCC_HSE_ON; +#endif +#endif + + /* + * HSI Oscillator (can be used as PLL and SYSCLK clock source). It is + * already turned on by default but a new calibration setting might be + * used. If the user chooses to turn it off, it must be turned off after + * SYSCLK was updated to use HSE/PLL. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSI) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI; + osc_init.HSIState = RCC_HSI_ON; + /* HSI calibration is not optional when HSI is enabled */ + osc_init.HSICalibrationValue = MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION); + +#if MYNEWT_VAL(STM32_CLOCK_HSI) && \ + !IS_RCC_HSICALIBRATION_VALUE(MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION)) +#error "Invalid HSI calibration value" +#endif +#endif + + /* + * Default to HSE as source, when both HSE and HSI are enabled. + * + * TODO: option to let the PLL turned off could be added, because + * both HSI and HSE can be used as SYSCLK source. + */ + osc_init.PLL.PLLState = RCC_PLL_ON; +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE; +#else + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSI; +#endif + +#if !IS_RCC_PLLM_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLM)) +#error "PLLM value is invalid" +#endif + +#if !IS_RCC_PLLN_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLN)) +#error "PLLN value is invalid" +#endif + +/* + * Redefine this macro for F7, because the Cube HAL is using typecast which + * is not valid when trying to catch errors at build time. + */ +#if MYNEWT_VAL(MCU_STM32F7) +#undef IS_RCC_PLLP_VALUE +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || \ + ((VALUE) == 6U) || ((VALUE) == 8U)) +#endif + +#if !IS_RCC_PLLP_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLP)) +#error "PLLP value is invalid" +#endif + +#if !IS_RCC_PLLQ_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ)) +#error "PLLQ value is invalid" +#endif + + osc_init.PLL.PLLM = MYNEWT_VAL(STM32_CLOCK_PLL_PLLM); + osc_init.PLL.PLLN = MYNEWT_VAL(STM32_CLOCK_PLL_PLLN); + osc_init.PLL.PLLP = MYNEWT_VAL(STM32_CLOCK_PLL_PLLP); + osc_init.PLL.PLLQ = MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ); + +#if MYNEWT_VAL(STM32_CLOCK_PLL_PLLR) + +#if !IS_RCC_PLLR_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLR)) +#error "PLLR value is invalid" +#endif + + osc_init.PLL.PLLR = MYNEWT_VAL(STM32_CLOCK_PLL_PLLR); + osc_init.PLL.PLLRGE = MYNEWT_VAL(STM32_CLOCK_PLL_PLLR); +#endif /* MYNEWT_VAL(STM32_CLOCK_PLL_PLLR) */ + + status = HAL_RCC_OscConfig(&osc_init); + if (status != HAL_OK) { + assert(0); + } + +#if MYNEWT_VAL(STM32_CLOCK_ENABLE_OVERDRIVE) + /* + * Activate the Over-Drive mode + */ + status = HAL_PWREx_EnableOverDrive(); + if (status != HAL_OK) { + assert(0); + } +#endif + + /* + * Select PLL as system clock source and configure the HCLK, PCLK1 and + * PCLK2 clocks dividers. HSI and HSE are also valid system clock sources, + * although there is no much point in supporting them now. + */ + clk_init.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + +#if !IS_RCC_HCLK(MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER)) +#error "AHB clock divider is invalid" +#endif + +#if !IS_RCC_PCLK1(MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER)) +#error "APB1 clock divider is invalid" +#endif + +#if !IS_RCC_PCLK1(MYNEWT_VAL(STM32_CLOCK_APB2_DIVIDER)) Review Comment: APB2 seems to have separate check IS_RCC_PCLK2 ########## hw/bsp/nucleo-h723zg/src/hal_bsp.c: ########## @@ -0,0 +1,279 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "spiflash/spiflash.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32h723xx.h> +#include <stm32_common/stm32_hal.h> +#include <bus/drivers/spi_common.h> + +#if MYNEWT_VAL(ETH_0) +#include <stm32_eth/stm32_eth.h> +#include <stm32_eth/stm32_eth_cfg.h> +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM11, + .irq = TIM1_TRG_COM_TIM11_IRQn, +}; +#endif + +int dupa = 6; Review Comment: Variable not used ########## hw/bsp/nucleo-h723zg/syscfg.yml: ########## @@ -0,0 +1,78 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + STM32_FLASH_SIZE_KB: + description: 'Total flash size in KB.' + value: 1024 + + STM32_FLASH_NUM_AREAS: + description: 'Number of flash sectors for a non-linear STM32 MCU.' + value: 12 + + BSP_FLASH_SPI_BUS: + description: 'bus name SPIFLASH is connected to' + value: '"spi0"' + + BSP_FLASH_SPI_NAME: + description: 'SPIFLASH device name' + value: '"spiflash0"' + +syscfg.vals: + REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG + CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS + NFFS_FLASH_AREA: FLASH_AREA_NFFS + COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1 + STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE0' + STM32_CLOCK_HSI: 1 + STM32_CLOCK_HSE: 0 + STM32_CLOCK_HSE_BYPASS: 0 + STM32_CLOCK_PLL_PLLM: 4 + STM32_CLOCK_PLL_PLLN: 34 + STM32_CLOCK_PLL_PLLP: 1 + STM32_CLOCK_PLL_PLLQ: 4 + STM32_CLOCK_PLL_PLLR: 2 + STM32_CLOCK_ENABLE_OVERDRIVE: 0 + STM32_CLOCK_AHB_DIVIDER: 'RCC_HCLK_DIV2' + STM32_CLOCK_APB1_DIVIDER: 'RCC_APB1_DIV4' + STM32_CLOCK_APB2_DIVIDER: 'RCC_APB1_DIV2' Review Comment: Maye RCC_APB**2**_DIV2 ########## hw/mcu/stm/stm32h7xx/src/clock_stm32h7xx.c: ########## @@ -0,0 +1,279 @@ +/* + * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "stm32h7xx_hal_pwr_ex.h" +#include "stm32h7xx_hal.h" +#include <assert.h> + +/* + * This allows an user to have a custom clock configuration by zeroing + * every possible clock source in the syscfg. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) || MYNEWT_VAL(STM32_CLOCK_LSE) || \ + MYNEWT_VAL(STM32_CLOCK_HSI) || MYNEWT_VAL(STM32_CLOCK_LSI) + +/* + * HSI is turned on by default, but can be turned off and use HSE instead. + */ +#if (((MYNEWT_VAL(STM32_CLOCK_HSE) != 0) + (MYNEWT_VAL(STM32_CLOCK_HSI) != 0)) < 1) +#error "At least one of HSE or HSI clock source must be enabled" +#endif + +void +SystemClock_Config(void) +{ + RCC_OscInitTypeDef osc_init = {0}; + RCC_ClkInitTypeDef clk_init = {0}; + HAL_StatusTypeDef status; + + + /* Enable the MCU instruction cache */ +#if MYNEWT_VAL(STM32_ENABLE_ICACHE) + SCB_EnableICache(); +#endif + + /* + * Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /* + * The voltage scaling allows optimizing the power consumption when the + * device is clocked below the maximum system frequency, to update the + * voltage scaling value regarding system frequency refer to product + * datasheet. + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(MYNEWT_VAL(STM32_CLOCK_VOLTAGESCALING_CONFIG)); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE; + + /* + * LSI is used to clock the independent watchdog and optionally the RTC. + * It can be disabled per user request, but is automatically enabled again + * when the IWDG is started. + * + * XXX currently the watchdog is not optional, so there's no point in + * disabling LSI through syscfg. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSI; +#if MYNEWT_VAL(STM32_CLOCK_LSI) + osc_init.LSIState = RCC_LSI_ON; +#else + osc_init.LSIState = RCC_LSI_OFF; +#endif + + /* + * LSE is only used to clock the RTC. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSE; +#if (MYNEWT_VAL(STM32_CLOCK_LSE) == 0) + osc_init.LSEState = RCC_LSE_OFF; +#elif MYNEWT_VAL(STM32_CLOCK_LSE_BYPASS) + osc_init.LSEState = RCC_LSE_BYPASS; +#else + osc_init.LSEState = RCC_LSE_ON; +#endif + + /* + * HSE Oscillator (can be used as PLL, SYSCLK and RTC clock source) + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE; +#if MYNEWT_VAL(STM32_CLOCK_HSE_BYPASS) + osc_init.HSEState = RCC_HSE_BYPASS; +#else + osc_init.HSEState = RCC_HSE_ON; +#endif +#endif + + /* + * HSI Oscillator (can be used as PLL and SYSCLK clock source). It is + * already turned on by default but a new calibration setting might be + * used. If the user chooses to turn it off, it must be turned off after + * SYSCLK was updated to use HSE/PLL. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSI) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI; + osc_init.HSIState = RCC_HSI_ON; + /* HSI calibration is not optional when HSI is enabled */ + osc_init.HSICalibrationValue = MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION); + +#if MYNEWT_VAL(STM32_CLOCK_HSI) && \ + !IS_RCC_HSICALIBRATION_VALUE(MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION)) +#error "Invalid HSI calibration value" +#endif +#endif + + /* + * Default to HSE as source, when both HSE and HSI are enabled. + * + * TODO: option to let the PLL turned off could be added, because + * both HSI and HSE can be used as SYSCLK source. + */ + osc_init.PLL.PLLState = RCC_PLL_ON; +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE; +#else + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSI; +#endif + +#if !IS_RCC_PLLM_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLM)) +#error "PLLM value is invalid" +#endif + +#if !IS_RCC_PLLN_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLN)) +#error "PLLN value is invalid" +#endif + +/* + * Redefine this macro for F7, because the Cube HAL is using typecast which + * is not valid when trying to catch errors at build time. + */ +#if MYNEWT_VAL(MCU_STM32F7) +#undef IS_RCC_PLLP_VALUE +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || \ + ((VALUE) == 6U) || ((VALUE) == 8U)) +#endif + +#if !IS_RCC_PLLP_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLP)) +#error "PLLP value is invalid" +#endif + +#if !IS_RCC_PLLQ_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ)) +#error "PLLQ value is invalid" +#endif + + osc_init.PLL.PLLM = MYNEWT_VAL(STM32_CLOCK_PLL_PLLM); + osc_init.PLL.PLLN = MYNEWT_VAL(STM32_CLOCK_PLL_PLLN); + osc_init.PLL.PLLP = MYNEWT_VAL(STM32_CLOCK_PLL_PLLP); + osc_init.PLL.PLLQ = MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ); + +#if MYNEWT_VAL(STM32_CLOCK_PLL_PLLR) + +#if !IS_RCC_PLLR_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLR)) +#error "PLLR value is invalid" +#endif + + osc_init.PLL.PLLR = MYNEWT_VAL(STM32_CLOCK_PLL_PLLR); + osc_init.PLL.PLLRGE = MYNEWT_VAL(STM32_CLOCK_PLL_PLLR); +#endif /* MYNEWT_VAL(STM32_CLOCK_PLL_PLLR) */ + + status = HAL_RCC_OscConfig(&osc_init); + if (status != HAL_OK) { + assert(0); + } + +#if MYNEWT_VAL(STM32_CLOCK_ENABLE_OVERDRIVE) + /* + * Activate the Over-Drive mode + */ + status = HAL_PWREx_EnableOverDrive(); + if (status != HAL_OK) { + assert(0); + } +#endif + + /* + * Select PLL as system clock source and configure the HCLK, PCLK1 and + * PCLK2 clocks dividers. HSI and HSE are also valid system clock sources, + * although there is no much point in supporting them now. + */ + clk_init.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; Review Comment: missing spaces around | Usually | is placed at the end of line in mynewt code ########## hw/bsp/nucleo-h723zg/src/hal_bsp.c: ########## @@ -0,0 +1,279 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "spiflash/spiflash.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32h723xx.h> +#include <stm32_common/stm32_hal.h> +#include <bus/drivers/spi_common.h> + +#if MYNEWT_VAL(ETH_0) +#include <stm32_eth/stm32_eth.h> +#include <stm32_eth/stm32_eth_cfg.h> +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM11, + .irq = TIM1_TRG_COM_TIM11_IRQn, +}; +#endif + +int dupa = 6; + +/* FIXME: this works but shouldn't it be dual bank? */ +const uint32_t stm32_flash_sectors[] = { + 0x08000000, /* 32kB */ + 0x08008000, /* 32kB */ + 0x08010000, /* 32kB */ + 0x08018000, /* 32kB */ + 0x08020000, /* 128kB */ + 0x08040000, /* 256kB */ + 0x08080000, /* 256kB */ + 0x080c0000, /* 256kB */ + 0x08100000, /* 256kB */ + 0x08140000, /* 256kB */ + 0x08180000, /* 256kB */ + 0x081c0000, /* 256kB */ + 0x08200000, /* End of flash */ +}; + +#define SZ (sizeof(stm32_flash_sectors) / sizeof(stm32_flash_sectors[0])) +static_assert(MYNEWT_VAL(STM32_FLASH_NUM_AREAS) + 1 == SZ, + "STM32_FLASH_NUM_AREAS does not match flash sectors"); + +#if MYNEWT_VAL(UART_0) +const struct stm32_uart_cfg os_bsp_uart0_cfg = { + .suc_uart = USART3, + .suc_rcc_reg = &RCC->APB1LENR, + .suc_rcc_dev = RCC_APB1LENR_USART3EN, + .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART3, + .suc_irqn = USART3_IRQn, +}; +#endif + +#if MYNEWT_VAL(I2C_0) +/* + * The PB8 and PB9 pins are connected through jumpers in the board to + * both ADC_IN and I2C pins. To enable I2C functionality SB147/SB157 need + * to be removed (they are the default connections) and SB138/SB143 need + * to be shorted. + */ +const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = { + .hic_i2c = I2C1, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C1EN, + .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C1, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_1) +const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = { + .hic_i2c = I2C2, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C2EN, + .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C2, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_2) +const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = { + .hic_i2c = I2C3, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C3EN, + .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C3, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_3) +const struct stm32_hal_i2c_cfg os_bsp_i2c3_cfg = { + .hic_i2c = I2C4, + .hic_rcc_reg = &RCC->APB1ENR, Review Comment: APB4ENR ########## hw/bsp/nucleo-h723zg/src/hal_bsp.c: ########## @@ -0,0 +1,279 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "spiflash/spiflash.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32h723xx.h> +#include <stm32_common/stm32_hal.h> +#include <bus/drivers/spi_common.h> + +#if MYNEWT_VAL(ETH_0) +#include <stm32_eth/stm32_eth.h> +#include <stm32_eth/stm32_eth_cfg.h> +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM11, + .irq = TIM1_TRG_COM_TIM11_IRQn, +}; +#endif + +int dupa = 6; + +/* FIXME: this works but shouldn't it be dual bank? */ +const uint32_t stm32_flash_sectors[] = { + 0x08000000, /* 32kB */ + 0x08008000, /* 32kB */ + 0x08010000, /* 32kB */ + 0x08018000, /* 32kB */ + 0x08020000, /* 128kB */ + 0x08040000, /* 256kB */ + 0x08080000, /* 256kB */ + 0x080c0000, /* 256kB */ + 0x08100000, /* 256kB */ + 0x08140000, /* 256kB */ + 0x08180000, /* 256kB */ + 0x081c0000, /* 256kB */ + 0x08200000, /* End of flash */ +}; + +#define SZ (sizeof(stm32_flash_sectors) / sizeof(stm32_flash_sectors[0])) +static_assert(MYNEWT_VAL(STM32_FLASH_NUM_AREAS) + 1 == SZ, + "STM32_FLASH_NUM_AREAS does not match flash sectors"); + +#if MYNEWT_VAL(UART_0) +const struct stm32_uart_cfg os_bsp_uart0_cfg = { + .suc_uart = USART3, + .suc_rcc_reg = &RCC->APB1LENR, + .suc_rcc_dev = RCC_APB1LENR_USART3EN, + .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART3, + .suc_irqn = USART3_IRQn, +}; +#endif + +#if MYNEWT_VAL(I2C_0) +/* + * The PB8 and PB9 pins are connected through jumpers in the board to + * both ADC_IN and I2C pins. To enable I2C functionality SB147/SB157 need + * to be removed (they are the default connections) and SB138/SB143 need + * to be shorted. + */ +const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = { + .hic_i2c = I2C1, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C1EN, + .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C1, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ Review Comment: Values probably copied from other system, probably will not match comment. Same applies to all I2C configurations. ########## hw/mcu/stm/stm32h7xx/src/clock_stm32h7xx.c: ########## @@ -0,0 +1,279 @@ +/* + * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "stm32h7xx_hal_pwr_ex.h" +#include "stm32h7xx_hal.h" +#include <assert.h> + +/* + * This allows an user to have a custom clock configuration by zeroing + * every possible clock source in the syscfg. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) || MYNEWT_VAL(STM32_CLOCK_LSE) || \ + MYNEWT_VAL(STM32_CLOCK_HSI) || MYNEWT_VAL(STM32_CLOCK_LSI) + +/* + * HSI is turned on by default, but can be turned off and use HSE instead. + */ +#if (((MYNEWT_VAL(STM32_CLOCK_HSE) != 0) + (MYNEWT_VAL(STM32_CLOCK_HSI) != 0)) < 1) +#error "At least one of HSE or HSI clock source must be enabled" +#endif + +void +SystemClock_Config(void) +{ + RCC_OscInitTypeDef osc_init = {0}; + RCC_ClkInitTypeDef clk_init = {0}; + HAL_StatusTypeDef status; + + + /* Enable the MCU instruction cache */ +#if MYNEWT_VAL(STM32_ENABLE_ICACHE) + SCB_EnableICache(); +#endif + + /* + * Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /* + * The voltage scaling allows optimizing the power consumption when the + * device is clocked below the maximum system frequency, to update the + * voltage scaling value regarding system frequency refer to product + * datasheet. + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(MYNEWT_VAL(STM32_CLOCK_VOLTAGESCALING_CONFIG)); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE; + + /* + * LSI is used to clock the independent watchdog and optionally the RTC. + * It can be disabled per user request, but is automatically enabled again + * when the IWDG is started. + * + * XXX currently the watchdog is not optional, so there's no point in + * disabling LSI through syscfg. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSI; +#if MYNEWT_VAL(STM32_CLOCK_LSI) + osc_init.LSIState = RCC_LSI_ON; +#else + osc_init.LSIState = RCC_LSI_OFF; +#endif + + /* + * LSE is only used to clock the RTC. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSE; +#if (MYNEWT_VAL(STM32_CLOCK_LSE) == 0) + osc_init.LSEState = RCC_LSE_OFF; +#elif MYNEWT_VAL(STM32_CLOCK_LSE_BYPASS) + osc_init.LSEState = RCC_LSE_BYPASS; +#else + osc_init.LSEState = RCC_LSE_ON; +#endif + + /* + * HSE Oscillator (can be used as PLL, SYSCLK and RTC clock source) + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE; +#if MYNEWT_VAL(STM32_CLOCK_HSE_BYPASS) + osc_init.HSEState = RCC_HSE_BYPASS; +#else + osc_init.HSEState = RCC_HSE_ON; +#endif +#endif + + /* + * HSI Oscillator (can be used as PLL and SYSCLK clock source). It is + * already turned on by default but a new calibration setting might be + * used. If the user chooses to turn it off, it must be turned off after + * SYSCLK was updated to use HSE/PLL. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSI) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI; + osc_init.HSIState = RCC_HSI_ON; + /* HSI calibration is not optional when HSI is enabled */ + osc_init.HSICalibrationValue = MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION); + +#if MYNEWT_VAL(STM32_CLOCK_HSI) && \ + !IS_RCC_HSICALIBRATION_VALUE(MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION)) +#error "Invalid HSI calibration value" +#endif +#endif + + /* + * Default to HSE as source, when both HSE and HSI are enabled. + * + * TODO: option to let the PLL turned off could be added, because + * both HSI and HSE can be used as SYSCLK source. + */ + osc_init.PLL.PLLState = RCC_PLL_ON; +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE; +#else + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSI; +#endif + +#if !IS_RCC_PLLM_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLM)) +#error "PLLM value is invalid" +#endif + +#if !IS_RCC_PLLN_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLN)) +#error "PLLN value is invalid" +#endif + +/* + * Redefine this macro for F7, because the Cube HAL is using typecast which + * is not valid when trying to catch errors at build time. + */ +#if MYNEWT_VAL(MCU_STM32F7) +#undef IS_RCC_PLLP_VALUE +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || \ + ((VALUE) == 6U) || ((VALUE) == 8U)) +#endif + +#if !IS_RCC_PLLP_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLP)) +#error "PLLP value is invalid" +#endif + +#if !IS_RCC_PLLQ_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ)) +#error "PLLQ value is invalid" +#endif + + osc_init.PLL.PLLM = MYNEWT_VAL(STM32_CLOCK_PLL_PLLM); + osc_init.PLL.PLLN = MYNEWT_VAL(STM32_CLOCK_PLL_PLLN); + osc_init.PLL.PLLP = MYNEWT_VAL(STM32_CLOCK_PLL_PLLP); + osc_init.PLL.PLLQ = MYNEWT_VAL(STM32_CLOCK_PLL_PLLQ); + +#if MYNEWT_VAL(STM32_CLOCK_PLL_PLLR) + +#if !IS_RCC_PLLR_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLR)) +#error "PLLR value is invalid" +#endif + + osc_init.PLL.PLLR = MYNEWT_VAL(STM32_CLOCK_PLL_PLLR); + osc_init.PLL.PLLRGE = MYNEWT_VAL(STM32_CLOCK_PLL_PLLR); Review Comment: this should be: ```c osc_init.PLL.PLLRGE = MYNEWT_VAL(STM32_CLOCK_PLLRGE); ``` ########## hw/bsp/nucleo-h723zg/src/hal_bsp.c: ########## @@ -0,0 +1,279 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "spiflash/spiflash.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32h723xx.h> +#include <stm32_common/stm32_hal.h> +#include <bus/drivers/spi_common.h> + +#if MYNEWT_VAL(ETH_0) +#include <stm32_eth/stm32_eth.h> +#include <stm32_eth/stm32_eth_cfg.h> +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM11, + .irq = TIM1_TRG_COM_TIM11_IRQn, +}; +#endif + +int dupa = 6; + +/* FIXME: this works but shouldn't it be dual bank? */ +const uint32_t stm32_flash_sectors[] = { + 0x08000000, /* 32kB */ + 0x08008000, /* 32kB */ + 0x08010000, /* 32kB */ + 0x08018000, /* 32kB */ + 0x08020000, /* 128kB */ + 0x08040000, /* 256kB */ + 0x08080000, /* 256kB */ + 0x080c0000, /* 256kB */ + 0x08100000, /* 256kB */ + 0x08140000, /* 256kB */ + 0x08180000, /* 256kB */ + 0x081c0000, /* 256kB */ + 0x08200000, /* End of flash */ +}; + +#define SZ (sizeof(stm32_flash_sectors) / sizeof(stm32_flash_sectors[0])) +static_assert(MYNEWT_VAL(STM32_FLASH_NUM_AREAS) + 1 == SZ, + "STM32_FLASH_NUM_AREAS does not match flash sectors"); + +#if MYNEWT_VAL(UART_0) +const struct stm32_uart_cfg os_bsp_uart0_cfg = { + .suc_uart = USART3, + .suc_rcc_reg = &RCC->APB1LENR, + .suc_rcc_dev = RCC_APB1LENR_USART3EN, + .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART3, + .suc_irqn = USART3_IRQn, +}; +#endif + +#if MYNEWT_VAL(I2C_0) +/* + * The PB8 and PB9 pins are connected through jumpers in the board to + * both ADC_IN and I2C pins. To enable I2C functionality SB147/SB157 need + * to be removed (they are the default connections) and SB138/SB143 need + * to be shorted. + */ +const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = { + .hic_i2c = I2C1, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C1EN, + .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C1, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_1) +const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = { + .hic_i2c = I2C2, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C2EN, + .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C2, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_2) +const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = { + .hic_i2c = I2C3, + .hic_rcc_reg = &RCC->APB1ENR, Review Comment: APB1LENR ########## hw/bsp/nucleo-h723zg/nucleo-h723zg.ld: ########## @@ -0,0 +1,36 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/* Linker script for STM32F767 when running from flash and using the bootloader */ Review Comment: STM32H723 ########## hw/bsp/nucleo-h723zg/include/bsp/bsp.h: ########## @@ -0,0 +1,100 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#ifndef H_BSP_H +#define H_BSP_H + +#include <inttypes.h> +#include <mcu/mcu.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Define special stackos sections */ +#define sec_data_core __attribute__((section(".data.core"))) +#define sec_bss_core __attribute__((section(".bss.core"))) +#define sec_bss_nz_core __attribute__((section(".bss.core.nz"))) + +/* More convenient section placement macros. */ +#define bssnz_t sec_bss_nz_core + +extern uint8_t _ram_start; +extern uint8_t _dtcmram_start; +extern uint8_t _itcmram_start; +extern uint8_t _ram2_start; + +#define RAM_SIZE (16 * 1024) +#define RAM2_SIZE (16 * 1024) +#define DTCMRAM_SIZE (128 * 1024) +#define ITCMRAM_SIZE (16 * 1024) Review Comment: ``` #define RAM_SIZE (320 * 1024) #define RAM2_SIZE (32 * 1024) #define RAM3_SIZE (16 * 1024) #define DTCMRAM_SIZE (128 * 1024) #define ITCMRAM_SIZE (64 * 1024) ``` ########## hw/bsp/nucleo-h723zg/nucleo-h723zg.ld: ########## @@ -0,0 +1,36 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/* Linker script for STM32F767 when running from flash and using the bootloader */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 384K /* Image slot 1 */ + ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 64K + /* + * XXX: DTCM + SRAM1 + SRAM2 are mapped in contiguous areas, + * Could this simply be RAM at 0x20000000 with LENGTH=512k? + */ + DTCM (rwx) : ORIGIN = 0x24000000, LENGTH = 128K + RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 32K /* SRAM1 + SRAM2 */ Review Comment: This whole section should be changed. Based on what ST provides maybe change to something like that ```ld ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 384K /* Image slot 1 */ RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 320K /* AXI (128) + AXI/ITCM (192) */ RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 32K /* SRAM1 + SRMA2 */ RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 16K /* SRAM4 */ ``` ########## hw/mcu/stm/stm32h7xx/src/clock_stm32h7xx.c: ########## @@ -0,0 +1,279 @@ +/* + * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "stm32h7xx_hal_pwr_ex.h" +#include "stm32h7xx_hal.h" +#include <assert.h> + +/* + * This allows an user to have a custom clock configuration by zeroing + * every possible clock source in the syscfg. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) || MYNEWT_VAL(STM32_CLOCK_LSE) || \ + MYNEWT_VAL(STM32_CLOCK_HSI) || MYNEWT_VAL(STM32_CLOCK_LSI) + +/* + * HSI is turned on by default, but can be turned off and use HSE instead. + */ +#if (((MYNEWT_VAL(STM32_CLOCK_HSE) != 0) + (MYNEWT_VAL(STM32_CLOCK_HSI) != 0)) < 1) +#error "At least one of HSE or HSI clock source must be enabled" +#endif + +void +SystemClock_Config(void) +{ + RCC_OscInitTypeDef osc_init = {0}; + RCC_ClkInitTypeDef clk_init = {0}; + HAL_StatusTypeDef status; + + + /* Enable the MCU instruction cache */ +#if MYNEWT_VAL(STM32_ENABLE_ICACHE) + SCB_EnableICache(); +#endif + + /* + * Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /* + * The voltage scaling allows optimizing the power consumption when the + * device is clocked below the maximum system frequency, to update the + * voltage scaling value regarding system frequency refer to product + * datasheet. + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(MYNEWT_VAL(STM32_CLOCK_VOLTAGESCALING_CONFIG)); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE; + + /* + * LSI is used to clock the independent watchdog and optionally the RTC. + * It can be disabled per user request, but is automatically enabled again + * when the IWDG is started. + * + * XXX currently the watchdog is not optional, so there's no point in + * disabling LSI through syscfg. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSI; +#if MYNEWT_VAL(STM32_CLOCK_LSI) + osc_init.LSIState = RCC_LSI_ON; +#else + osc_init.LSIState = RCC_LSI_OFF; +#endif + + /* + * LSE is only used to clock the RTC. + */ + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSE; +#if (MYNEWT_VAL(STM32_CLOCK_LSE) == 0) + osc_init.LSEState = RCC_LSE_OFF; +#elif MYNEWT_VAL(STM32_CLOCK_LSE_BYPASS) + osc_init.LSEState = RCC_LSE_BYPASS; +#else + osc_init.LSEState = RCC_LSE_ON; +#endif + + /* + * HSE Oscillator (can be used as PLL, SYSCLK and RTC clock source) + */ +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE; +#if MYNEWT_VAL(STM32_CLOCK_HSE_BYPASS) + osc_init.HSEState = RCC_HSE_BYPASS; +#else + osc_init.HSEState = RCC_HSE_ON; +#endif +#endif + + /* + * HSI Oscillator (can be used as PLL and SYSCLK clock source). It is + * already turned on by default but a new calibration setting might be + * used. If the user chooses to turn it off, it must be turned off after + * SYSCLK was updated to use HSE/PLL. + */ +#if MYNEWT_VAL(STM32_CLOCK_HSI) + osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI; + osc_init.HSIState = RCC_HSI_ON; + /* HSI calibration is not optional when HSI is enabled */ + osc_init.HSICalibrationValue = MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION); + +#if MYNEWT_VAL(STM32_CLOCK_HSI) && \ + !IS_RCC_HSICALIBRATION_VALUE(MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION)) +#error "Invalid HSI calibration value" +#endif +#endif + + /* + * Default to HSE as source, when both HSE and HSI are enabled. + * + * TODO: option to let the PLL turned off could be added, because + * both HSI and HSE can be used as SYSCLK source. + */ + osc_init.PLL.PLLState = RCC_PLL_ON; +#if MYNEWT_VAL(STM32_CLOCK_HSE) + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE; +#else + osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSI; +#endif + +#if !IS_RCC_PLLM_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLM)) +#error "PLLM value is invalid" +#endif + +#if !IS_RCC_PLLN_VALUE(MYNEWT_VAL(STM32_CLOCK_PLL_PLLN)) +#error "PLLN value is invalid" +#endif + +/* + * Redefine this macro for F7, because the Cube HAL is using typecast which + * is not valid when trying to catch errors at build time. + */ +#if MYNEWT_VAL(MCU_STM32F7) +#undef IS_RCC_PLLP_VALUE +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || \ + ((VALUE) == 6U) || ((VALUE) == 8U)) +#endif Review Comment: Code looks like is intended for other MCU ########## hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c: ########## @@ -1,28 +1,28 @@ /** - * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include "os/mynewt.h" #include "mcu/stm32_hal.h" Review Comment: Whole file should preserve old formatting. It's hard to see what was changed. Format changes should be placed in separate commits if needed. ########## hw/mcu/stm/stm32_common/src/hal_watchdog.c: ########## @@ -36,7 +37,11 @@ hal_watchdog_init(uint32_t expire_msecs) return -1; } +#if !MYNEWT_VAL(MCU_STM32H7) g_wdt_cfg.Instance = IWDG; +#else + g_wdt_cfg.Instance = IWDG1; +#endif Review Comment: Reverse condition so there is not negative condition. Same applies to hal_watchdog_enable() ########## hw/bsp/nucleo-h723zg/include/bsp/stm32h7xx_hal_conf.h: ########## @@ -0,0 +1,422 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32h7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_HAL_CONF_H +#define __STM32H7xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CEC_MODULE_ENABLED +#define HAL_COMP_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DCMI_MODULE_ENABLED +#define HAL_DFSDM_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_DMA2D_MODULE_ENABLED +#define HAL_ETH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_FDCAN_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +#define HAL_HRTIM_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_JPEG_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_MDIOS_MODULE_ENABLED +#define HAL_MDMA_MODULE_ENABLED +#define HAL_MMC_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_OPAMP_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RAMECC_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_SDRAM_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_SMBUS_MODULE_ENABLED +#define HAL_SPDIFRX_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_SWPMI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ Review Comment: While oscillator X3 is not populated line PH0 line is connected to onboard STLink clock of 8MHz ########## hw/mcu/stm/stm32h7xx/src/system_stm32h7xx.c: ########## @@ -0,0 +1,447 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @version V1.2.0 + * @date 30-December-2016 + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> Review Comment: It probably would be better to use template provided by ST for H7 instead of copying from F7 ########## hw/bsp/nucleo-h723zg/src/hal_bsp.c: ########## @@ -0,0 +1,279 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include <assert.h> + +#include "bsp/bsp.h" +#include "os/mynewt.h" +#include "spiflash/spiflash.h" + +#include <hal/hal_bsp.h> +#include <hal/hal_flash_int.h> +#include <hal/hal_system.h> + +#include <stm32h723xx.h> +#include <stm32_common/stm32_hal.h> +#include <bus/drivers/spi_common.h> + +#if MYNEWT_VAL(ETH_0) +#include <stm32_eth/stm32_eth.h> +#include <stm32_eth/stm32_eth_cfg.h> +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include <pwm_stm32/pwm_stm32.h> +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM11, + .irq = TIM1_TRG_COM_TIM11_IRQn, +}; +#endif + +int dupa = 6; + +/* FIXME: this works but shouldn't it be dual bank? */ +const uint32_t stm32_flash_sectors[] = { + 0x08000000, /* 32kB */ + 0x08008000, /* 32kB */ + 0x08010000, /* 32kB */ + 0x08018000, /* 32kB */ + 0x08020000, /* 128kB */ + 0x08040000, /* 256kB */ + 0x08080000, /* 256kB */ + 0x080c0000, /* 256kB */ + 0x08100000, /* 256kB */ + 0x08140000, /* 256kB */ + 0x08180000, /* 256kB */ + 0x081c0000, /* 256kB */ + 0x08200000, /* End of flash */ +}; + +#define SZ (sizeof(stm32_flash_sectors) / sizeof(stm32_flash_sectors[0])) +static_assert(MYNEWT_VAL(STM32_FLASH_NUM_AREAS) + 1 == SZ, + "STM32_FLASH_NUM_AREAS does not match flash sectors"); + +#if MYNEWT_VAL(UART_0) +const struct stm32_uart_cfg os_bsp_uart0_cfg = { + .suc_uart = USART3, + .suc_rcc_reg = &RCC->APB1LENR, + .suc_rcc_dev = RCC_APB1LENR_USART3EN, + .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART3, + .suc_irqn = USART3_IRQn, +}; +#endif + +#if MYNEWT_VAL(I2C_0) +/* + * The PB8 and PB9 pins are connected through jumpers in the board to + * both ADC_IN and I2C pins. To enable I2C functionality SB147/SB157 need + * to be removed (they are the default connections) and SB138/SB143 need + * to be shorted. + */ +const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = { + .hic_i2c = I2C1, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C1EN, + .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C1, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_1) +const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = { + .hic_i2c = I2C2, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C2EN, + .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C2, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_2) +const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = { + .hic_i2c = I2C3, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C3EN, + .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C3, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_3) +const struct stm32_hal_i2c_cfg os_bsp_i2c3_cfg = { + .hic_i2c = I2C4, + .hic_rcc_reg = &RCC->APB1ENR, + .hic_rcc_dev = RCC_APB1ENR_I2C4EN, + .hic_pin_sda = MYNEWT_VAL(I2C_3_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_3_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C4, + .hic_10bit = 0, + .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(ETH_0) +const struct stm32_eth_cfg os_bsp_eth0_cfg = { + /* + * PORTA + * PA1 - ETH_RMII_REF_CLK + * PA2 - ETH_RMII_MDIO + * PA7 - ETH_RMII_CRS_DV + */ + .sec_port_mask[0] = (1 << 1) | (1 << 2) | (1 << 7), + + /* + * PORTB + * PB13 - ETH_RMII_TXD1 + */ + .sec_port_mask[1] = (1 << 13), + + /* + * PORTC + * PC1 - ETH_RMII_MDC + * PC4 - ETH_RMII_RXD0 + * PC5 - ETH_RMII_RXD1 + */ + .sec_port_mask[2] = (1 << 1) | (1 << 4) | (1 << 5), + + /* + * PORTG + * PG11 - ETH_RMII_TXEN + * PG13 - ETH_RMII_TXD0 + */ + .sec_port_mask[6] = (1 << 11) | (1 << 13), + .sec_phy_type = LAN_8742_RMII, + .sec_phy_irq = -1 +}; +#endif + +/* FIXME */ +static const struct hal_bsp_mem_dump dump_cfg[] = { + [0] = { + .hbmd_start = &_ram_start, + .hbmd_size = RAM_SIZE, + }, + [1] = { + .hbmd_start = &_dtcmram_start, Review Comment: _ram_start and _dtcmram_start point to same address ########## hw/mcu/stm/stm32h7xx/syscfg.yml: ########## @@ -0,0 +1,140 @@ +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + MCU_FLASH_MIN_WRITE_SIZE: + description: > + Specifies the required alignment for internal flash writes. + Used internally by the newt tool. + value: 1 + + MCU_STM32H7: + description: MCUs are of STM32H7xx family + value: 1 + + STM32_ENABLE_ICACHE: + description: Enable instruction caching + value: 1 + + STM32_CLOCK_VOLTAGESCALING_CONFIG: + description: Voltage scale + value: 0 + + STM32_CLOCK_LSI: + description: Enable low-speed internal clock source + value: 1 + + STM32_CLOCK_LSE: + description: Enable low-speed external clock source (aka RTC xtal) + value: 0 + + STM32_CLOCK_LSE_BYPASS: + description: 0 for 32768 xtal; 1 for input clock + value: 0 + + STM32_CLOCK_HSE: + description: Enable high-speed external clock source + value: 0 + + STM32_CLOCK_HSE_BYPASS: + description: 0 for xtal; 1 for input clock + value: 0 + + STM32_CLOCK_HSI: + description: Enable high-speed internal clock source + value: 1 + + STM32_CLOCK_HSI_CALIBRATION: + description: HSI calibration value + value: 'RCC_HSICALIBRATION_DEFAULT' + + STM32_CLOCK_PLL_PLLM: + description: PLL config M parameter + value: 0 + + STM32_CLOCK_PLL_PLLN: + description: PLL config N parameter + value: 0 + + STM32_CLOCK_PLL_PLLP: + description: PLL config P parameter + value: 0 + + STM32_CLOCK_PLL_PLLQ: + description: PLL config Q parameter + value: 0 + + STM32_CLOCK_PLL_PLLR: + description: PLL config R parameter + value: 0 + + STM32_CLOCK_PLLRGE: + description: PLL input frequency range + value: 0 + + STM32_CLOCK_ENABLE_OVERDRIVE: + description: Turn on over-drive mode (reach higher clock rates) + value: 0 + + STM32_CLOCK_AHB_DIVIDER: + description: AHB prescaler + value: 0 + + STM32_CLOCK_APB1_DIVIDER: + description: APB low-speed prescaler + value: 0 + + STM32_CLOCK_APB2_DIVIDER: + description: APB high-speed prescaler + value: 0 + + STM32_CLOCK_APB3_DIVIDER: + description: APB low-speed prescaler + value: 0 + + STM32_CLOCK_APB4_DIVIDER: + description: APB high-speed prescaler + value: 0 + + STM32_FLASH_LATENCY: + description: Number of wait-states + value: 0 + + STM32_ART_ACCLERATOR_ENABLE: + description: Enable ... + value: 0 + + STM32_FLASH_PREFETCH_ENABLE: Review Comment: Does not seem to be used anywhere ########## hw/mcu/stm/stm32h7xx/syscfg.yml: ########## @@ -0,0 +1,140 @@ +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + MCU_FLASH_MIN_WRITE_SIZE: + description: > + Specifies the required alignment for internal flash writes. + Used internally by the newt tool. + value: 1 + + MCU_STM32H7: + description: MCUs are of STM32H7xx family + value: 1 + + STM32_ENABLE_ICACHE: + description: Enable instruction caching + value: 1 + + STM32_CLOCK_VOLTAGESCALING_CONFIG: + description: Voltage scale + value: 0 + + STM32_CLOCK_LSI: + description: Enable low-speed internal clock source + value: 1 + + STM32_CLOCK_LSE: + description: Enable low-speed external clock source (aka RTC xtal) + value: 0 + + STM32_CLOCK_LSE_BYPASS: + description: 0 for 32768 xtal; 1 for input clock + value: 0 + + STM32_CLOCK_HSE: + description: Enable high-speed external clock source + value: 0 + + STM32_CLOCK_HSE_BYPASS: + description: 0 for xtal; 1 for input clock + value: 0 + + STM32_CLOCK_HSI: + description: Enable high-speed internal clock source + value: 1 + + STM32_CLOCK_HSI_CALIBRATION: + description: HSI calibration value + value: 'RCC_HSICALIBRATION_DEFAULT' + + STM32_CLOCK_PLL_PLLM: + description: PLL config M parameter + value: 0 + + STM32_CLOCK_PLL_PLLN: + description: PLL config N parameter + value: 0 + + STM32_CLOCK_PLL_PLLP: + description: PLL config P parameter + value: 0 + + STM32_CLOCK_PLL_PLLQ: + description: PLL config Q parameter + value: 0 + + STM32_CLOCK_PLL_PLLR: + description: PLL config R parameter + value: 0 + + STM32_CLOCK_PLLRGE: + description: PLL input frequency range + value: 0 + + STM32_CLOCK_ENABLE_OVERDRIVE: + description: Turn on over-drive mode (reach higher clock rates) + value: 0 + + STM32_CLOCK_AHB_DIVIDER: + description: AHB prescaler + value: 0 + + STM32_CLOCK_APB1_DIVIDER: + description: APB low-speed prescaler + value: 0 + + STM32_CLOCK_APB2_DIVIDER: + description: APB high-speed prescaler + value: 0 + + STM32_CLOCK_APB3_DIVIDER: + description: APB low-speed prescaler + value: 0 + + STM32_CLOCK_APB4_DIVIDER: + description: APB high-speed prescaler + value: 0 + + STM32_FLASH_LATENCY: + description: Number of wait-states + value: 0 + + STM32_ART_ACCLERATOR_ENABLE: Review Comment: Not used -- This is an automated message from the Apache Git Service. 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