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The following commit(s) were added to refs/heads/master by this push: new 4e2b2ff kernel/arch: Add option to use BASEPRI for critical section 4e2b2ff is described below commit 4e2b2ffa26a48d5b9cb48406cd0660117dcb4e18 Author: Andrzej Kaczmarek <andrzej.kaczma...@codecoup.pl> AuthorDate: Tue Mar 3 20:27:24 2020 +0100 kernel/arch: Add option to use BASEPRI for critical section This adds "hidden" option to use BASEPRI instead of PRIMASK for critical sections on supported MCUs (i.e. Cortex M3/4/7/33). New behavior can be enabled by #define in mcu/mcu.h as follows: MCU_CRITICAL_BASEPRI <x> where <x> is highest priority interrupt that should be disabled by critical section. Note that priority values here are the same as for NVIC_SetPriority, i.e. they are *not* shifted by number of unused priority bits. --- kernel/os/src/arch/cortex_m3/os_arch_arm.c | 25 ++++++++++++++++++++----- kernel/os/src/arch/cortex_m33/os_arch_arm.c | 25 ++++++++++++++++++++----- kernel/os/src/arch/cortex_m4/os_arch_arm.c | 25 ++++++++++++++++++++----- kernel/os/src/arch/cortex_m7/os_arch_arm.c | 25 ++++++++++++++++++++----- 4 files changed, 80 insertions(+), 20 deletions(-) diff --git a/kernel/os/src/arch/cortex_m3/os_arch_arm.c b/kernel/os/src/arch/cortex_m3/os_arch_arm.c index bc9f0e6..40be88b 100644 --- a/kernel/os/src/arch/cortex_m3/os_arch_arm.c +++ b/kernel/os/src/arch/cortex_m3/os_arch_arm.c @@ -127,26 +127,41 @@ os_arch_save_sr(void) { uint32_t isr_ctx; - isr_ctx = __get_PRIMASK(); +#if MCU_CRITICAL_BASEPRI + isr_ctx = __get_BASEPRI(); + __set_BASEPRI((MCU_CRITICAL_BASEPRI) << (8 - __NVIC_PRIO_BITS)); +#else + isr_ctx = __get_PRIMASK() & 1; __disable_irq(); - return (isr_ctx & 1); +#endif + + return isr_ctx; } void os_arch_restore_sr(os_sr_t isr_ctx) { +#if MCU_CRITICAL_BASEPRI + __set_BASEPRI(isr_ctx); +#else if (!isr_ctx) { __enable_irq(); } +#endif } int os_arch_in_critical(void) { - uint32_t isr_ctx; + int ret; + +#if MCU_CRITICAL_BASEPRI + ret = __get_BASEPRI() > 0; +#else + ret = __get_PRIMASK() & 1; +#endif - isr_ctx = __get_PRIMASK(); - return (isr_ctx & 1); + return ret; } static void diff --git a/kernel/os/src/arch/cortex_m33/os_arch_arm.c b/kernel/os/src/arch/cortex_m33/os_arch_arm.c index e33d8dc..03677c7 100644 --- a/kernel/os/src/arch/cortex_m33/os_arch_arm.c +++ b/kernel/os/src/arch/cortex_m33/os_arch_arm.c @@ -128,26 +128,41 @@ os_arch_save_sr(void) { uint32_t isr_ctx; - isr_ctx = __get_PRIMASK(); +#if MCU_CRITICAL_BASEPRI + isr_ctx = __get_BASEPRI(); + __set_BASEPRI((MCU_CRITICAL_BASEPRI) << (8 - __NVIC_PRIO_BITS)); +#else + isr_ctx = __get_PRIMASK() & 1; __disable_irq(); - return (isr_ctx & 1); +#endif + + return isr_ctx; } void os_arch_restore_sr(os_sr_t isr_ctx) { +#if MCU_CRITICAL_BASEPRI + __set_BASEPRI(isr_ctx); +#else if (!isr_ctx) { __enable_irq(); } +#endif } int os_arch_in_critical(void) { - uint32_t isr_ctx; + int ret; + +#if MCU_CRITICAL_BASEPRI + ret = __get_BASEPRI() > 0; +#else + ret = __get_PRIMASK() & 1; +#endif - isr_ctx = __get_PRIMASK(); - return (isr_ctx & 1); + return ret; } static void diff --git a/kernel/os/src/arch/cortex_m4/os_arch_arm.c b/kernel/os/src/arch/cortex_m4/os_arch_arm.c index 26de0f5..48111e5 100644 --- a/kernel/os/src/arch/cortex_m4/os_arch_arm.c +++ b/kernel/os/src/arch/cortex_m4/os_arch_arm.c @@ -128,26 +128,41 @@ os_arch_save_sr(void) { uint32_t isr_ctx; - isr_ctx = __get_PRIMASK(); +#if MCU_CRITICAL_BASEPRI + isr_ctx = __get_BASEPRI(); + __set_BASEPRI((MCU_CRITICAL_BASEPRI) << (8 - __NVIC_PRIO_BITS)); +#else + isr_ctx = __get_PRIMASK() & 1; __disable_irq(); - return (isr_ctx & 1); +#endif + + return isr_ctx; } void os_arch_restore_sr(os_sr_t isr_ctx) { +#if MCU_CRITICAL_BASEPRI + __set_BASEPRI(isr_ctx); +#else if (!isr_ctx) { __enable_irq(); } +#endif } int os_arch_in_critical(void) { - uint32_t isr_ctx; + int ret; + +#if MCU_CRITICAL_BASEPRI + ret = __get_BASEPRI() > 0; +#else + ret = __get_PRIMASK() & 1; +#endif - isr_ctx = __get_PRIMASK(); - return (isr_ctx & 1); + return ret; } static void diff --git a/kernel/os/src/arch/cortex_m7/os_arch_arm.c b/kernel/os/src/arch/cortex_m7/os_arch_arm.c index 26de0f5..48111e5 100644 --- a/kernel/os/src/arch/cortex_m7/os_arch_arm.c +++ b/kernel/os/src/arch/cortex_m7/os_arch_arm.c @@ -128,26 +128,41 @@ os_arch_save_sr(void) { uint32_t isr_ctx; - isr_ctx = __get_PRIMASK(); +#if MCU_CRITICAL_BASEPRI + isr_ctx = __get_BASEPRI(); + __set_BASEPRI((MCU_CRITICAL_BASEPRI) << (8 - __NVIC_PRIO_BITS)); +#else + isr_ctx = __get_PRIMASK() & 1; __disable_irq(); - return (isr_ctx & 1); +#endif + + return isr_ctx; } void os_arch_restore_sr(os_sr_t isr_ctx) { +#if MCU_CRITICAL_BASEPRI + __set_BASEPRI(isr_ctx); +#else if (!isr_ctx) { __enable_irq(); } +#endif } int os_arch_in_critical(void) { - uint32_t isr_ctx; + int ret; + +#if MCU_CRITICAL_BASEPRI + ret = __get_BASEPRI() > 0; +#else + ret = __get_PRIMASK() & 1; +#endif - isr_ctx = __get_PRIMASK(); - return (isr_ctx & 1); + return ret; } static void