updated PIC32 to use custom startup code
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/0163ea6c Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/0163ea6c Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/0163ea6c Branch: refs/heads/bluetooth5 Commit: 0163ea6cbf5b2ee95b118da7448e03eecacc3d7a Parents: b022ac7 Author: julian <julian.ing...@imgtec.com> Authored: Fri Apr 28 10:48:43 2017 +0100 Committer: julian <julian.ing...@imgtec.com> Committed: Thu May 4 16:58:45 2017 +0100 ---------------------------------------------------------------------- compiler/xc32/compiler.yml | 4 +- compiler/xc32/pkg.yml | 3 + hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c | 2 +- hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c | 2 +- .../src/arch/cortex_m4/startup_STM32F429x.s | 3 - .../arch/pic32/startup/cache-err-exception.S | 129 ++++ kernel/os/src/arch/pic32/startup/crt0.S | 623 +++++++++++++++++++ .../src/arch/pic32/startup/general-exception.S | 141 +++++ .../pic32/startup/simple-tlb-refill-exception.S | 135 ++++ .../stubs/default-bootstrap-exception-handler.c | 58 ++ .../stubs/default-cache-err-exception-handler.c | 56 ++ .../stubs/default-general-exception-handler.c | 54 ++ .../src/arch/pic32/stubs/default-nmi-handler.S | 63 ++ .../src/arch/pic32/stubs/default-on-bootstrap.c | 43 ++ .../os/src/arch/pic32/stubs/default-on-reset.c | 43 ++ ...efault-simple-tlb-refill-exception-handler.c | 56 ++ .../os/src/arch/pic32/stubs/pic32_init_cache.S | 299 +++++++++ .../arch/pic32/stubs/pic32_init_tlb_ebi_sqi.S | 145 +++++ kernel/os/src/arch/pic32/stubs/sbrk.c | 305 +++++++++ 19 files changed, 2157 insertions(+), 7 deletions(-) ---------------------------------------------------------------------- http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/compiler/xc32/compiler.yml ---------------------------------------------------------------------- diff --git a/compiler/xc32/compiler.yml b/compiler/xc32/compiler.yml index 611497e..fcd4a91 100644 --- a/compiler/xc32/compiler.yml +++ b/compiler/xc32/compiler.yml @@ -24,13 +24,13 @@ compiler.path.objdump: "xc32-objdump" compiler.path.objsize: "xc32-size" compiler.path.objcopy: "xc32-objcopy" -compiler.flags.base: -std=gnu11 +compiler.flags.base: -std=gnu11 -msmart-io=0 compiler.flags.default: [compiler.flags.base, -O2, -g3] compiler.flags.optimized: [compiler.flags.base, -Os -g3] compiler.flags.debug: [compiler.flags.base, -g3] compiler.as.flags: [-x, assembler-with-cpp] -compiler.ld.flags: +compiler.ld.flags: -nostartfiles -nostdlib -static-libgcc -lgcc compiler.ld.resolve_circular_deps: true compiler.ld.mapfile: true http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/compiler/xc32/pkg.yml ---------------------------------------------------------------------- diff --git a/compiler/xc32/pkg.yml b/compiler/xc32/pkg.yml index 94b8c44..ef99ff5 100644 --- a/compiler/xc32/pkg.yml +++ b/compiler/xc32/pkg.yml @@ -25,3 +25,6 @@ pkg.homepage: "http://mynewt.apache.org/" pkg.keywords: - pic32 - compiler + +pkg.deps: + - libc/baselibc http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c ---------------------------------------------------------------------- diff --git a/hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c b/hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c index c1187c6..87fcfa6 100644 --- a/hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c +++ b/hw/bsp/pic32mx470_6lp_clicker/src/hal_bsp.c @@ -21,7 +21,7 @@ #include <assert.h> const struct hal_flash * -bsp_flash_dev(uint8_t id) +hal_bsp_flash_dev(uint8_t id) { return 0; } http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c ---------------------------------------------------------------------- diff --git a/hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c b/hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c index c1187c6..87fcfa6 100644 --- a/hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c +++ b/hw/bsp/pic32mz2048_wi-fire/src/hal_bsp.c @@ -21,7 +21,7 @@ #include <assert.h> const struct hal_flash * -bsp_flash_dev(uint8_t id) +hal_bsp_flash_dev(uint8_t id) { return 0; } http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/hw/bsp/stm32f429discovery/src/arch/cortex_m4/startup_STM32F429x.s ---------------------------------------------------------------------- diff --git a/hw/bsp/stm32f429discovery/src/arch/cortex_m4/startup_STM32F429x.s b/hw/bsp/stm32f429discovery/src/arch/cortex_m4/startup_STM32F429x.s index f1bdc8a..8174e5f 100644 --- a/hw/bsp/stm32f429discovery/src/arch/cortex_m4/startup_STM32F429x.s +++ b/hw/bsp/stm32f429discovery/src/arch/cortex_m4/startup_STM32F429x.s @@ -556,6 +556,3 @@ g_pfnVectors: .thumb_set DMA2D_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/startup/cache-err-exception.S ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/startup/cache-err-exception.S b/kernel/os/src/arch/pic32/startup/cache-err-exception.S new file mode 100644 index 0000000..ec35687 --- /dev/null +++ b/kernel/os/src/arch/pic32/startup/cache-err-exception.S @@ -0,0 +1,129 @@ +/********************************************************************* + * + * Cache Error Exception + * + ********************************************************************* + * Filename: cache-err-exception.S + * + * Processor: PIC32 + * + * Compiler: MPLAB XC32 v1.00 + * MPLAB X IDE + * Company: Microchip Technology Inc. + * + * Software License Agreement + * + * Copyright (c) 2014, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its + * subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Microchip's name may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************/ + +#include <xc.h> +#ifdef __LIBBUILD__ + .file 1 "cache-err-exception.S" + .loc 1 0 +#endif + ################### + # Default Simple TLB-Refill handler + ################### + + .weak __exception_handler_break + + .section .text._cache_err_exception_context, code + .set noreorder + .set noat + .set nomips16 + .globl _cache_err_exception_context + .ent _cache_err_exception_context + +_cache_err_exception_context: + + # Save off the non-callee saved registers that may get mucked with + addiu sp, sp, -88 + sw $1, 4(sp) + sw v0, 8(sp) + sw v1, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw t0, 32(sp) + sw t1, 36(sp) + sw t2, 40(sp) + sw t3, 44(sp) + sw t4, 48(sp) + sw t5, 52(sp) + sw t6, 56(sp) + sw t7, 60(sp) + sw t8, 64(sp) + sw t9, 68(sp) + sw ra, 72(sp) + mflo t0 + sw t0, 76(sp) + mfhi t0 + sw t0, 80(sp) + + # Pass Cause and Status to the handler function +0: mfc0 a0, _CP0_CAUSE + mfc0 a1, _CP0_STATUS + la v0, _cache_err_exception_handler + jalr v0 + nop + + lw t0, 80(sp) + mthi t0 + lw t0, 76(sp) + mtlo t0 + + lw $1, 4(sp) + lw v0, 8(sp) + lw v1, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw t0, 32(sp) + lw t1, 36(sp) + lw t2, 40(sp) + lw t3, 44(sp) + lw t4, 48(sp) + lw t5, 52(sp) + lw t6, 56(sp) + lw t7, 60(sp) + lw t8, 64(sp) + lw t9, 68(sp) + lw ra, 72(sp) + addiu sp, sp, 88 + + ehb + eret + + .end _cache_err_exception_context + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/startup/crt0.S ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/startup/crt0.S b/kernel/os/src/arch/pic32/startup/crt0.S new file mode 100644 index 0000000..88397d2 --- /dev/null +++ b/kernel/os/src/arch/pic32/startup/crt0.S @@ -0,0 +1,623 @@ +/********************************************************************* + * + * C Runtime Startup + * + ********************************************************************* + * Filename: crt0.S + * + * Processor: PIC32 + * + * Compiler: MPLAB XC32 + * MPLAB X IDE + * Company: Microchip Technology Inc. + * + * Software License Agreement + * + * Copyright (c) 2014, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its + * subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Microchip's name may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************/ + +#include "xc.h" +#include <cp0defs.h> + +#ifdef __LIBBUILD__ + # Replace the standard debugging information with a simple filename. This + # prevents the library build directory from showing up in MPLAB IDE. It + # also effectively disables source-line debugging. + .file 1 "libpic32/startup/crt0.S" + .loc 1 0 +#endif + +#if (__XC32_VERSION > 1000) && !defined(CPP_INIT) +#define CPP_INIT +#endif + +#if !defined(PIC32_SRS_SET_COUNT) +# if defined(__PIC32_SRS_SET_COUNT) +# define PIC32_SRS_SET_COUNT __PIC32_SRS_SET_COUNT +# else +# warning PIC32_SRS_SET_COUNT not defined on build line +# define PIC32_SRS_SET_COUNT 2 +# endif +#endif + +#if defined(__PIC32MX) || defined(__PIC32MM) || defined(__PIC32MZ) +#define INIT_DATA 1 +#endif + +/* This file contains 32-bit assembly code */ + .set nomips16 + + ################################################################## + # Entry point of the entire application + ################################################################## + .section .reset,code,keep + .align 2 + .set noreorder + .ent _reset + +############################ +# Begin ISA switching code # +############################ + +#if defined (__mips_micromips) + .set micromips +#endif + +#if (defined(__PIC32_HAS_MICROMIPS)) && (defined(__PIC32_HAS_MIPS32R2)) +_reset: + .word 0x10000003 /* MIPS32: branch forward 0x10 bytes from here */ + /* MicroMIPS: ADDI32 $0, $0, 0x0007 (nop) */ + /* DO NOT change the relative branch */ + + .word 0x00000000 /* NOP */ +__reset_micromips_isa: + .set micromips + jal _startup + nop + + .align 2 + /* Device not in proper ISA mode */ + .set nomicromips +__reset_switch_isa: + jal _startup + nop + +#else + +_reset: + jal _startup + nop + +#endif /* __PIC32_HAS_MICROMIPS */ + + .align 2 + .end _reset + .globl _reset + .size _reset, .-_reset + + .section .reset.startup,code,keep + .align 2 + .set noreorder + +#if defined (__mips_micromips) + .set micromips +#else + .set nomicromips +#endif + +############################ +# End ISA switching code # +############################ + + ################################################################## + # Startup code + ################################################################## + .align 2 + .globl _startup + .set noreorder + .ent _startup +_startup: + ################################################################## + # If entered because of an NMI, jump to the NMI handler. + ################################################################## + mfc0 k0,_CP0_STATUS + ext k0,k0,19,1 # Extract NMI bit + beqz k0,_no_nmi + nop + la k0,_nmi_handler + jr k0 + nop +_no_nmi: + + ################################################################## + # Initialize Stack Pointer + # _stack is initialized by the linker script to point to the + # starting location of the stack in DRM + ################################################################## + la sp,_stack + + ################################################################## + # Initialize Global Pointer + # _gp is initialized by the linker script to point to "middle" + # of the small variables region + ################################################################## + la gp,_gp + +#if (PIC32_SRS_SET_COUNT == 2) + ################################################################## + # Initialize Global Pointer in Shadow Set + # The SRSCtl's PSS field must be set to the shadow set in which + # to initialize the global pointer. Since we have only a + # single shadow set (besides the normal), we will initialize + # SRSCtl<PSS> to SRSCtl<HSS>. We then write the global pointer + # to the previous shadow set to ensure that on interrupt, the + # global pointer has been initialized. + ################################################################## + mfc0 t1,_CP0_SRSCTL # Read SRSCtl register + add t3,t1,zero # Save off current SRSCtl + ext t2,t1,26,4 # to obtain HSS field + ins t1,t2,6,4 # Put HSS field + mtc0 t1,_CP0_SRSCTL # into SRSCtl<PSS> + ehb # Clear hazard before using new SRSCTL + wrpgpr gp,gp # Set global pointer in PSS + mtc0 t3,_CP0_SRSCTL # Restore SRSCtl + ehb + +#elif (PIC32_SRS_SET_COUNT > 2) + ################################################################## + # Initialize Global Pointer in Shadow Set(s) + # The SRSCtl PSS field must be set to the shadow set in which + # to initialize the global pointer. We will initialize + # SRSCtl<PSS> to the number of reg sets and work down to set zero. + # We write the global pointer to the previous shadow set to + # ensure that on interrupt, the global pointer has been + # initialized. + ################################################################## + mfc0 t1,_CP0_SRSCTL # Read SRSCtl register + add t3,t1,zero # Save off current SRSCtl + + li t2,(PIC32_SRS_SET_COUNT-1) + +1: ins t1,t2,6,4 # Put next shadow set field + mtc0 t1,_CP0_SRSCTL # into SRSCtl<PSS> + ehb # Clear hazard before using new SRSCTL + wrpgpr gp,gp # Set global pointer in PSS + + addiu t2,t2,-1 # Next lower shadow set + # Loop for all sets + bne t2,$0,1b # Down to zero (normal GPR set) + nop + + mtc0 t3,_CP0_SRSCTL # Restore SRSCtl + ehb + +#endif /* (PIC32_SRS_SET_COUNT > 2) */ + + ################################################################## + # Call the "on reset" procedure + ################################################################## + la t0,_on_reset + jalr t0 + nop + +#if defined(INIT_MMU_MZ_FIXED) || defined(__PIC32_HAS_MMU_MZ_FIXED) + ################################################################## + # Initialize TLB for fixed mapping to EBI and SQI + ################################################################## + .extern __pic32_tlb_init_ebi_sqi + la t0,__pic32_tlb_init_ebi_sqi + jalr t0 + nop +#endif + +#if defined(INIT_L1_CACHE) || defined(__PIC32_HAS_L1CACHE) + ################################################################## + # Initialize L1 cache register + ################################################################## + .extern __pic32_init_cache + + la t0,__pic32_init_cache + jalr t0 + nop +#endif + + ################################################################## + # Clear uninitialized data sections + ################################################################## +_start_bss_init: + la t0,_bss_begin + la t1,_bss_end + b _bss_check + nop + +_bss_init: + sw zero,0x0(t0) + sw zero,0x4(t0) + sw zero,0x8(t0) + sw zero,0xc(t0) + addu t0,16 +_bss_check: + bltu t0,t1,_bss_init + nop + +#if defined(INIT_DATA) || defined(__PIC32_HAS_INIT_DATA) + ################################################################## + # Initialize data using the linker-generated .dinit table + ################################################################## + .equiv FMT_CLEAR,0 + .equiv FMT_COPY,1 +_dinit_init: + la t0,_dinit_addr + +#define SRC t0 +#define DST t1 +#define LEN t2 +#define FMT t3 + +0: lw DST,0(SRC) + beqz DST,9f + addu SRC,4 + lw LEN,0(SRC) + addu SRC,4 + lw FMT,0(SRC) + beq FMT,$0,_dinit_clear + addu SRC,4 + +_dinit_copy: + lbu t4,0(SRC) + subu LEN,1 + addu SRC,1 + sb t4,0(DST) + bne LEN,$0,_dinit_copy + addu DST,1 + + b _dinit_end + nop + +_dinit_clear: + sb $0,(DST) + subu LEN,1 + bne LEN,$0,_dinit_clear + addu DST,1 + +_dinit_end: + addu SRC,3 + addiu LEN,$0,0xFFFFFFFC + and SRC,LEN,SRC + lw DST,0(SRC) + bne DST,$0,0b + nop +9: + +#endif /* INIT_DATA */ + + ################################################################## + # If there are no RAM functions, skip the next section -- + # initializing bus matrix registers. + ################################################################## + la t1,_ramfunc_begin + beqz t1,_ramfunc_done + nop + +#if defined(INIT_SSX) || defined(__PIC32_HAS_SSX) + /* No initialization required */ +#else /* Use BMX */ + ################################################################## + # Initialize bus matrix registers if RAM functions exist in the + # application + ################################################################## + la t1,_bmxdkpba_address + la t2,BMXDKPBA + sw t1,0(t2) + la t1,_bmxdudba_address + la t2,BMXDUDBA + sw t1,0(t2) + la t1,_bmxdupba_address + la t2,BMXDUPBA + sw t1,0(t2) +#endif /* INIT_SSX */ + +_ramfunc_done: + + ################################################################## + # Initialize CP0 registers + ################################################################## + # Initialize Count register + ################################################################## + mtc0 zero,_CP0_COUNT + + ################################################################## + # Initialize Compare register + ################################################################## + li t2,-1 + mtc0 t2,_CP0_COMPARE + + ################################################################## + # Ensure BEV set and Initialize EBase register + ################################################################## + li t0, (1<<22) + mfc0 t2,_CP0_STATUS + or t2,t0,t2 # Set BEV bit 22 + mtc0 t2,_CP0_STATUS + + la t1,_ebase_address + ehb + mtc0 t1,_CP0_EBASE + + ################################################################## + # Initialize PRISS register to a safer default for devices that + # have it. The application should re-initialize it to an + # application-specific value. + # + # We do NOT do this by default. + ################################################################## +#if defined(USE_DEFAULT_PRISS_VALUE) +#if defined(_PRISS_PRI7SS_POSITION) +#if (PIC32_SRS_SET_COUNT >= 7) + li t2, 0x76540000 + addiu t2, t2, 0x3210 + lui t1, %hi(PRISS) + sw t2, %lo(PRISS)(t1) +#elif (PIC32_SRS_SET_COUNT <= 2) + li t2, 0x10000000 + lui t1, %hi(PRISS) + sw t2, %lo(PRISS)(t1) +#endif /* PIC32_SRS_SET_COUNT */ +#endif /* _PRISS_PRI7SS_POSITION */ +#endif /* USE_DEFAULT_PRISS_VALUE */ + + ################################################################## + # Initialize IntCtl/INTCON.VS register with _vector_spacing + ################################################################## + la t1,_vector_spacing +#if defined(INIT_INTCONVS) || defined(__PIC32_HAS_INTCONVS) + la t0, INTCON + lw t2, 0(t0) + li t2, 0 + ins t2, t1, 16, 7 +#if defined(__PIC32MM) && defined(_INTCON_MVEC_MASK) + ori t2, t2, _INTCON_MVEC_MASK +#endif + sw t2, 0(t0) +#endif + li t2,0 # Clear t2 and + ins t2,t1,5,5 # shift value to VS field + mtc0 t2,_CP0_INTCTL + + ################################################################## + # Initialize CAUSE registers + # - Enable counting of Count register <DC = 0> + # - Use special exception vector <IV = 1> + # - Clear pending software interrupts <IP1:IP0 = 0> + ################################################################## + li t1,0x00800000 + mtc0 t1,_CP0_CAUSE + + ################################################################## + # Initialize STATUS register + # - Access to Coprocessor 0 not allowed in user mode <CU0 = 0> + # - User mode uses configured endianness <RE = 0> + # - Preserve Bootstrap Exception vectors <BEV> + # - Preserve soft reset <SR> and non-maskable interrupt <NMI> + # - CorExtend enabled based on whether CorExtend User Defined + # Instructions have been implemented <CEE = Config<UDI>> + # - Disable any pending interrupts <IM7..IM2 = 0, IM1..IM0 = 0> + # - Disable hardware interrupts <IPL7:IPL2 = 0> + # - Base mode is Kernel mode <UM = 0> + # - Error level is normal <ERL = 0> + # - Exception level is normal <EXL = 0> + # - Interrupts are disabled <IE = 0> + # - DSPr2 ASE is enabled for devices that support it <MX = 1> + # - FPU64 is enabled for devices that support it <CU1=1> & <FR=1> + ################################################################## + mfc0 t0,_CP0_CONFIG + ext t1,t0,22,1 # Extract UDI from Config register + sll t1,t1,17 # Move UDI to Status.CEE location + mfc0 t0,_CP0_STATUS + and t0,t0,0x00580000 # Preserve SR, NMI, and BEV +#if defined(INIT_DSPR2) || defined(__PIC32_HAS_DSPR2) + li t2, 0x01000000 # Set the Status.MX bit to enable DSP + or t0,t2,t0 +#endif +#if defined(INIT_FPU64) || defined(__PIC32_HAS_FPU64) + li t2, 0x24000000 # Set the Status.CU1 and Status.FR bits to + or t0,t2,t0 # enable the FPU in FR64 mode +#endif + + or t0,t1,t0 # Include Status.CEE (from UDI) + mtc0 t0,_CP0_STATUS + +#if defined(PIC32WK) && defined(_CP0_CONFIG3) && defined (__mips_micromips) + # Ensure that the ISAONEXEC bit is set for the microMIPS ISA for the PIC32WK family + # _bsc0 (_CP0_CONFIG3, _CP0_CONFIG3_SELECT, ISAONEXEC_MASK) + li t1,0x10000 # ISAONEXEC bit + mfc0 t0,_CP0_CONFIG3 + or t1,t0,t1 + mtc0 t1,_CP0_CONFIG3 + +#endif /* PIC32WK && __mips_micromips */ + +#if defined(INIT_FPU64) || defined(__PIC32_HAS_FPU64) + # FPU Control and Status + li t2,0x1000000 # FCSR: RM=0, FS=1, FO=0, FN=0 + # Enables: 0b00000 E=1, V=0, Z=0, O=0, U=0, I=0 + ctc1 t2, $31 # High perf on denormal operands & tiny results +#endif + ehb + + ################################################################## + # Call the "on bootstrap" procedure + ################################################################## + la t0,_on_bootstrap + jalr t0 + nop + + ################################################################## + # Initialize Status<BEV> for normal exception vectors + ################################################################## + mfc0 t0,_CP0_STATUS + and t0,t0,0xffbfffff # Clear BEV + mtc0 t0,_CP0_STATUS + + ################################################################## + # Call main. We do this via a thunk in the text section so that + # a normal jump and link can be used, enabling the startup code + # to work properly whether main is written in MIPS16 or MIPS32 + # code. I.e., the linker will correctly adjust the JAL to JALX if + # necessary + ################################################################## + and a0,a0,0 + and a1,a1,0 + la t0,_main_entry + jr t0 + nop + + .end _startup + + ################################################################## + # Boot Exception Vector Handler + # Jumps to _bootstrap_exception_handler + ################################################################## + .section .bev_handler,code,keep + .align 2 + .set noreorder + .ent _bev_exception +_bev_exception: + la k0,_bootstrap_exception_handler + jr k0 + nop + + .end _bev_exception + + ################################################################## + # General Exception Vector Handler + # Jumps to _general_exception_context + ################################################################## + .section .gen_handler,code + .align 2 + .set noreorder + .ent _gen_exception +_gen_exception: +0: la k0,_general_exception_context + jr k0 + nop + + .end _gen_exception + +#if defined(INIT_MMU_MZ_FIXED) || defined(__PIC32_HAS_MMU_MZ_FIXED) + ################################################################## + # Simple TLB-Refill Exception Vector + # Jumps to _simple_tlb_refill_exception_context + ################################################################## + .section .simple_tlb_refill_vector,code,keep + .align 2 + .set noreorder + .ent simple_tlb_refill_vector +simple_tlb_refill_vector: + la k0,_simple_tlb_refill_exception_context + jr k0 + nop + + .end simple_tlb_refill_vector +#endif + +#if defined(INIT_L1_CACHE) || defined(__PIC32_HAS_L1CACHE) + ################################################################## + # Cache-Error Exception Vector Handler + # Jumps to _cache_err_exception_context + ################################################################## + .section .cache_err_vector,code,keep + .align 2 + .set noreorder + .ent _cache_err_vector +_cache_err_vector: + la k0,_cache_err_exception_context + jr k0 + nop + + .end _cache_err_vector +#endif + + .section .text.main_entry,code,keep + .align 2 + .ent _main_entry +_main_entry: + +#if defined(CPP_INIT) + .weak _init + # call .init section to run constructors etc + lui a0,%hi(_init) + addiu sp,sp,-24 + addiu a0,a0,%lo(_init) + beq a0,$0,2f + sw $31,20(sp) #, + jalr a0 + nop +2: +#endif + and a0,a0,0 + and a1,a1,0 + + ################################################################## + + # Call _start + ################################################################## + la t0,_start + jalr t0 + nop + +#if defined(CALL_EXIT) + ################################################################## + # Call exit() + ################################################################## + jal exit + nop +#endif + + ################################################################## + # Just in case, go into infinite loop + # Call a software breakpoint only with -mdebugger compiler option + ################################################################## + .weak __exception_handler_break +__crt0_exit: +1: + la v0,__exception_handler_break + beq v0,0,0f + nop + jalr v0 + nop + +0: b 1b + nop + + .globl __crt0_exit + .end _main_entry http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/startup/general-exception.S ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/startup/general-exception.S b/kernel/os/src/arch/pic32/startup/general-exception.S new file mode 100644 index 0000000..ce30284 --- /dev/null +++ b/kernel/os/src/arch/pic32/startup/general-exception.S @@ -0,0 +1,141 @@ +/********************************************************************* + * + * General Exception + * + ********************************************************************* + * Filename: general-exception.S + * + * Processor: PIC32 + * + * Compiler: MPLAB XC32 v1.00 + * MPLAB X IDE + * Company: Microchip Technology Inc. + * + * Software License Agreement + * + * Copyright (c) 2014, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its + * subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Microchip's name may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************/ + +#include <xc.h> +#ifdef __LIBBUILD__ + .file 1 "general-exception.S" + .loc 1 0 +#endif + ################### + # Default general exception handler + ################### + + .extern _general_exception_handler + + .section .text.general_exception, code + .set noreorder + .set noat + .set nomips16 + .globl _general_exception_context + .ent _general_exception_context + +_general_exception_context: + + # Save off the non-callee saved registers that may get mucked with + addiu sp, sp, -88 + sw $1, 4(sp) + sw v0, 8(sp) + sw v1, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw t0, 32(sp) + sw t1, 36(sp) + sw t2, 40(sp) + sw t3, 44(sp) + sw t4, 48(sp) + sw t5, 52(sp) + sw t6, 56(sp) + sw t7, 60(sp) + sw t8, 64(sp) + sw t9, 68(sp) + sw ra, 72(sp) + mflo t0 + sw t0, 76(sp) + mfhi t0 + sw t0, 80(sp) + +#if defined(__PIC__) + lw t9,%call16(_general_exception_handler)(gp) + nop + # Pass Cause and Status to the handler function + mfc0 a0, _CP0_CAUSE + mfc0 a1, _CP0_STATUS + jalr t9 + nop +#else + la k0,_general_exception_handler + nop + + # Pass Cause and Status to the handler function + mfc0 a0, _CP0_CAUSE + mfc0 a1, _CP0_STATUS + jalr k0 + nop +#endif + + lw t0, 80(sp) + mthi t0 + lw t0, 76(sp) + mtlo t0 + + lw $1, 4(sp) + lw v0, 8(sp) + lw v1, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw t0, 32(sp) + lw t1, 36(sp) + lw t2, 40(sp) + lw t3, 44(sp) + lw t4, 48(sp) + lw t5, 52(sp) + lw t6, 56(sp) + lw t7, 60(sp) + lw t8, 64(sp) + lw t9, 68(sp) + lw ra, 72(sp) + addiu sp, sp, 88 + + ehb + eret + + .end _general_exception_context + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/startup/simple-tlb-refill-exception.S ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/startup/simple-tlb-refill-exception.S b/kernel/os/src/arch/pic32/startup/simple-tlb-refill-exception.S new file mode 100644 index 0000000..900d129 --- /dev/null +++ b/kernel/os/src/arch/pic32/startup/simple-tlb-refill-exception.S @@ -0,0 +1,135 @@ +/********************************************************************* + * + * Simple TLB-Refill Exception + * + ********************************************************************* + * Filename: simple-tlb-refill-exception.S + * + * Processor: PIC32 + * + * Compiler: MPLAB XC32 v1.00 + * MPLAB X IDE + * Company: Microchip Technology Inc. + * + * Software License Agreement + * + * Copyright (c) 2014, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its + * subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Microchip's name may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************/ + +#include <xc.h> +#ifdef __LIBBUILD__ + .file 1 "simple-tlb-refill-exception.S" + .loc 1 0 +#endif + ################### + # Default Simple TLB-Refill handler + ################### + + .weak __exception_handler_break + + .section .text.simple_tlb_refill_context, code + .set noreorder + .set noat + .set nomips16 + .globl _simple_tlb_refill_exception_context + .ent _simple_tlb_refill_exception_context + +_simple_tlb_refill_exception_context: + + # Save off the non-callee saved registers that may get mucked with + addiu sp, sp, -88 + sw $1, 4(sp) + sw v0, 8(sp) + sw v1, 12(sp) + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + sw t0, 32(sp) + sw t1, 36(sp) + sw t2, 40(sp) + sw t3, 44(sp) + sw t4, 48(sp) + sw t5, 52(sp) + sw t6, 56(sp) + sw t7, 60(sp) + sw t8, 64(sp) + sw t9, 68(sp) + sw ra, 72(sp) + mflo t0 + sw t0, 76(sp) + mfhi t0 + sw t0, 80(sp) + + # Pass Cause and Status to the handler function +0: mfc0 a0, _CP0_CAUSE + mfc0 a1, _CP0_STATUS +#if defined(__PIC__) + lw t9, %call16(_simple_tlb_refill_exception_handler)(gp) + jalr t9 + nop +#else + la v0, _simple_tlb_refill_exception_handler + jalr v0 + nop +#endif + + lw t0, 80(sp) + mthi t0 + lw t0, 76(sp) + mtlo t0 + + lw $1, 4(sp) + lw v0, 8(sp) + lw v1, 12(sp) + lw a0, 16(sp) + lw a1, 20(sp) + lw a2, 24(sp) + lw a3, 28(sp) + lw t0, 32(sp) + lw t1, 36(sp) + lw t2, 40(sp) + lw t3, 44(sp) + lw t4, 48(sp) + lw t5, 52(sp) + lw t6, 56(sp) + lw t7, 60(sp) + lw t8, 64(sp) + lw t9, 68(sp) + lw ra, 72(sp) + addiu sp, sp, 88 + + ehb # do we need this? Execution hazard barriers? + eret + + .end _simple_tlb_refill_exception_context + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/stubs/default-bootstrap-exception-handler.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/stubs/default-bootstrap-exception-handler.c b/kernel/os/src/arch/pic32/stubs/default-bootstrap-exception-handler.c new file mode 100644 index 0000000..9b582b9 --- /dev/null +++ b/kernel/os/src/arch/pic32/stubs/default-bootstrap-exception-handler.c @@ -0,0 +1,58 @@ +/********************************************************************* + * + * Default Bootstrap Exception Handler Implementation + * + ********************************************************************* + * Filename: default-bootstrap-exception-handler.c + * + * Processor: PIC32 + * + * Compiler: MPLAB C Compiler for PIC32 MCUs + * MPLAB IDE + * Company: Microchip Technology Inc. + * + * Software License Agreement + * + * The software supplied herewith by Microchip Technology Incorporated + * (the 'Company') for its PIC32/PIC24F Microcontroller is intended + * and supplied to you, the Company's customer, for use solely and + * exclusively on Microchip PIC32/PIC24F Microcontroller products. + * The software is owned by the Company and/or its supplier, and is + * protected under applicable copyright laws. All rights are reserved. + * Any use in violation of the foregoing restrictions may subject the + * user to criminal sanctions under applicable laws, as well as to + * civil liability for the breach of the terms and conditions of this + * license. + * + * THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED + * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, + * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ********************************************************************/ + +/* This is a default definition of a bootstrap exception handler function. + * It does nothing and just does a software reset. If the user + * application supplies a handler function, this function will not be + * referenced and thus not pulled in from the library. + */ + +extern void __attribute__((nomips16, noreturn, far, weak)) __pic32_software_reset(); +void __attribute__((weak)) __exception_handler_break(void); +extern void _DEBUGGER __attribute__((weak)); + +void +__attribute__((weak, nomips16, noreturn)) _bootstrap_exception_handler (void) +{ + if (&_DEBUGGER != 0 && __exception_handler_break) + __asm__ volatile ("sdbbp 0"); + + if (__pic32_software_reset) + __pic32_software_reset(); + + while(1); +} + + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/stubs/default-cache-err-exception-handler.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/stubs/default-cache-err-exception-handler.c b/kernel/os/src/arch/pic32/stubs/default-cache-err-exception-handler.c new file mode 100644 index 0000000..1f0f008 --- /dev/null +++ b/kernel/os/src/arch/pic32/stubs/default-cache-err-exception-handler.c @@ -0,0 +1,56 @@ +/********************************************************************* + * + * Default Cache-Error Exception Handler Implementation + * + ********************************************************************* + * Filename: default-cache-err-exception-handler.c + * + * Processor: PIC32 + * + * Compiler: MPLAB C Compiler for PIC32 MCUs + * MPLAB IDE + * Company: Microchip Technology Inc. + * + * Software License Agreement + * + * The software supplied herewith by Microchip Technology Incorporated + * (the 'Company') for its PIC32/PIC24F Microcontroller is intended + * and supplied to you, the Company's customer, for use solely and + * exclusively on Microchip PIC32/PIC24F Microcontroller products. + * The software is owned by the Company and/or its supplier, and is + * protected under applicable copyright laws. All rights are reserved. + * Any use in violation of the foregoing restrictions may subject the + * user to criminal sanctions under applicable laws, as well as to + * civil liability for the breach of the terms and conditions of this + * license. + * + * THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED + * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, + * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ********************************************************************/ +/* This is a default definition of a cache-error exception handler function. + * It does nothing and just does a software reset. If the user + * application supplies a handler function, this function will not be + * referenced and thus not pulled in from the library. + */ + +extern void __attribute__((nomips16, noreturn, far, weak)) __pic32_software_reset(); +void __attribute__((weak)) __exception_handler_break(void); +extern void _DEBUGGER __attribute__((weak)); + +void +__attribute__((weak, nomips16, noreturn)) _cache_err_exception_handler (void) +{ + if (&_DEBUGGER != 0 && __exception_handler_break) + __asm__ volatile ("sdbbp 0"); + + if (__pic32_software_reset) + __pic32_software_reset(); + + while(1); +} + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/stubs/default-general-exception-handler.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/stubs/default-general-exception-handler.c b/kernel/os/src/arch/pic32/stubs/default-general-exception-handler.c new file mode 100644 index 0000000..ed71330 --- /dev/null +++ b/kernel/os/src/arch/pic32/stubs/default-general-exception-handler.c @@ -0,0 +1,54 @@ +/********************************************************************* + * + * Default General Exception Handler Implementation + * + ********************************************************************* + * Filename: default-general-exception-handler.c + * + * Processor: PIC32 + * + * Compiler: MPLAB C Compiler for PIC32 MCUs + * MPLAB IDE + * Company: Microchip Technology Inc. + * + * Software License Agreement + * + * The software supplied herewith by Microchip Technology Incorporated + * (the 'Company') for its PIC32/PIC24F Microcontroller is intended + * and supplied to you, the Company's customer, for use solely and + * exclusively on Microchip PIC32/PIC24F Microcontroller products. + * The software is owned by the Company and/or its supplier, and is + * protected under applicable copyright laws. All rights are reserved. + * Any use in violation of the foregoing restrictions may subject the + * user to criminal sanctions under applicable laws, as well as to + * civil liability for the breach of the terms and conditions of this + * license. + * + * THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED + * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, + * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ********************************************************************/ +/* This is a default definition of a general exception handler function. + * It does nothing and just does a software reset. If the user + * application supplies a handler function, this function will not be + * referenced and thus not pulled in from the library. + */ +extern void __attribute__((nomips16, noreturn, far, weak)) __pic32_software_reset(); +void __attribute__((weak)) __exception_handler_break(void); +extern void _DEBUGGER __attribute__((weak)); + +void +__attribute__((weak, nomips16, noreturn)) _general_exception_handler (void) +{ + if (&_DEBUGGER != 0 && __exception_handler_break) + __asm__ volatile ("sdbbp 0"); + + if (__pic32_software_reset) + __pic32_software_reset(); + + while(1); +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/stubs/default-nmi-handler.S ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/stubs/default-nmi-handler.S b/kernel/os/src/arch/pic32/stubs/default-nmi-handler.S new file mode 100644 index 0000000..5d14c2f --- /dev/null +++ b/kernel/os/src/arch/pic32/stubs/default-nmi-handler.S @@ -0,0 +1,63 @@ +/********************************************************************* + * + * Default NMI Handler Implementation + * + ********************************************************************* + * Filename: default-nmi-handler.S + * + * Processor: PIC32 + * + * Compiler: MPLAB XC32 + * MPLAB X IDE + * Company: Microchip Technology Inc. + * + * Software License Agreement + * + * The software supplied herewith by Microchip Technology Incorporated + * (the 'Company') for its PIC32/PIC24F Microcontroller is intended + * and supplied to you, the Company's customer, for use solely and + * exclusively on Microchip PIC32/PIC24F Microcontroller products. + * The software is owned by the Company and/or its supplier, and is + * protected under applicable copyright laws. All rights are reserved. + * Any use in violation of the foregoing restrictions may subject the + * user to criminal sanctions under applicable laws, as well as to + * civil liability for the breach of the terms and conditions of this + * license. + * + * THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED + * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, + * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ********************************************************************/ + +#include <xc.h> +#ifdef __LIBBUILD__ + .file 1 "Microchip PIC32 Library" + .loc 1 0 +#endif + .text + .align 2 + .weak _nmi_handler + .set nomips16 + .ent _nmi_handler +_nmi_handler: + .frame sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + + mfc0 k0, _CP0_STATUS # retrieve STATUS + lui k1, ~(_CP0_STATUS_BEV_MASK >> 16) & 0xffff + ori k1, k1, ~_CP0_STATUS_BEV_MASK & 0xffff + and k0, k0, k1 # Clear BEV + mtc0 k0, _CP0_STATUS # store STATUS + eret + + .set macro + .set reorder + .end _nmi_handler + .size _nmi_handler, .-_nmi_handler + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/stubs/default-on-bootstrap.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/stubs/default-on-bootstrap.c b/kernel/os/src/arch/pic32/stubs/default-on-bootstrap.c new file mode 100644 index 0000000..442816d --- /dev/null +++ b/kernel/os/src/arch/pic32/stubs/default-on-bootstrap.c @@ -0,0 +1,43 @@ +/********************************************************************* + * + * Default _on_bootstrap Implementation + * + ********************************************************************* + * Filename: default-on-bootstrap.c + * + * Processor: PIC32 + * + * Compiler: MPLAB C Compiler for PIC32 MCUs + * MPLAB IDE + * Company: Microchip Technology Inc. + * + * Software License Agreement + * + * The software supplied herewith by Microchip Technology Incorporated + * (the 'Company') for its PIC32/PIC24F Microcontroller is intended + * and supplied to you, the Company's customer, for use solely and + * exclusively on Microchip PIC32/PIC24F Microcontroller products. + * The software is owned by the Company and/or its supplier, and is + * protected under applicable copyright laws. All rights are reserved. + * Any use in violation of the foregoing restrictions may subject the + * user to criminal sanctions under applicable laws, as well as to + * civil liability for the breach of the terms and conditions of this + * license. + * + * THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED + * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, + * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ********************************************************************/ +/* This is a default definition of an _on_bootstrap() function. + * It does nothing and just goes returns. If the user + * application supplies a handler function, this function will not be + * referenced and thus not pulled in from the library. + */ +void +__attribute__((weak)) _on_bootstrap (void) +{ +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/stubs/default-on-reset.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/stubs/default-on-reset.c b/kernel/os/src/arch/pic32/stubs/default-on-reset.c new file mode 100644 index 0000000..9a11b33 --- /dev/null +++ b/kernel/os/src/arch/pic32/stubs/default-on-reset.c @@ -0,0 +1,43 @@ +/********************************************************************* + * + * Default _on_reset Implementation + * + ********************************************************************* + * Filename: default-on-reset.c + * + * Processor: PIC32 + * + * Compiler: MPLAB C Compiler for PIC32 MCUs + * MPLAB IDE + * Company: Microchip Technology Inc. + * + * Software License Agreement + * + * The software supplied herewith by Microchip Technology Incorporated + * (the 'Company') for its PIC32/PIC24F Microcontroller is intended + * and supplied to you, the Company's customer, for use solely and + * exclusively on Microchip PIC32/PIC24F Microcontroller products. + * The software is owned by the Company and/or its supplier, and is + * protected under applicable copyright laws. All rights are reserved. + * Any use in violation of the foregoing restrictions may subject the + * user to criminal sanctions under applicable laws, as well as to + * civil liability for the breach of the terms and conditions of this + * license. + * + * THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED + * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, + * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ********************************************************************/ +/* This is a default definition of an _on_reset() function. + * It does nothing and just goes returns. If the user + * application supplies a handler function, this function will not be + * referenced and thus not pulled in from the library. + */ +void +__attribute__((weak)) _on_reset (void) +{ +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/stubs/default-simple-tlb-refill-exception-handler.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/stubs/default-simple-tlb-refill-exception-handler.c b/kernel/os/src/arch/pic32/stubs/default-simple-tlb-refill-exception-handler.c new file mode 100644 index 0000000..4ede8f7 --- /dev/null +++ b/kernel/os/src/arch/pic32/stubs/default-simple-tlb-refill-exception-handler.c @@ -0,0 +1,56 @@ +/********************************************************************* + * + * Default Simple TLB-Refill Exception Handler Implementation + * + ********************************************************************* + * Filename: default-simple-tlb-refill-exception-handler.c + * + * Processor: PIC32 + * + * Compiler: MPLAB C Compiler for PIC32 MCUs + * MPLAB IDE + * Company: Microchip Technology Inc. + * + * Software License Agreement + * + * The software supplied herewith by Microchip Technology Incorporated + * (the 'Company') for its PIC32/PIC24F Microcontroller is intended + * and supplied to you, the Company's customer, for use solely and + * exclusively on Microchip PIC32/PIC24F Microcontroller products. + * The software is owned by the Company and/or its supplier, and is + * protected under applicable copyright laws. All rights are reserved. + * Any use in violation of the foregoing restrictions may subject the + * user to criminal sanctions under applicable laws, as well as to + * civil liability for the breach of the terms and conditions of this + * license. + * + * THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED + * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, + * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ********************************************************************/ +/* This is a default definition of a simple tlb-refill exception handler function. + * It does nothing and just does a software reset. If the user + * application supplies a handler function, this function will not be + * referenced and thus not pulled in from the library. + */ + +extern void __attribute__((nomips16, noreturn, far, weak)) __pic32_software_reset(); +void __attribute__((weak)) __exception_handler_break(void); +extern void _DEBUGGER __attribute__((weak)); + +void +__attribute__((weak, nomips16, noreturn)) _simple_tlb_refill_exception_handler (void) +{ + if (&_DEBUGGER != 0 && __exception_handler_break) + __asm__ volatile ("sdbbp 0"); + + if (__pic32_software_reset) + __pic32_software_reset(); + + while(1); +} + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/stubs/pic32_init_cache.S ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/stubs/pic32_init_cache.S b/kernel/os/src/arch/pic32/stubs/pic32_init_cache.S new file mode 100644 index 0000000..af7cd68 --- /dev/null +++ b/kernel/os/src/arch/pic32/stubs/pic32_init_cache.S @@ -0,0 +1,299 @@ +/*------------------------------------------------------------------------- + * + * Copyright (c) 2014, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its + * subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. Microchip's name may not be used to endorse or promote products + * derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *-------------------------------------------------------------------------*/ + +#include <xc.h> +#include <cp0defs.h> + + /* Symbols defined in linker script */ + .weak __pic32_init_cache_program_base_addr + .weak __pic32_init_cache_data_base_addr + +/* Cache Coherency Attributes */ +#define _CACHE_WRITEBACK_WRITEALLOCATE 3 +#define _CACHE_WRITETHROUGH_WRITEALLOCATE 1 +#define _CACHE_WRITETHROUGH_NOWRITEALLOCATE 0 +#define _CACHE_DISABLE 2 + +#ifndef _CP0_ERRCTL +#define _CP0_ERRCTL $26, 0 +#endif + +#ifndef _CP0_TAGLO +#define _CP0_TAGLO $28, 0 +#endif + +/* Set __PIC32_CACHE_MODE to the desired coherency attribute */ +#define __PIC32_CACHE_MODE _CACHE_WRITEBACK_WRITEALLOCATE + +/* ==================================== */ +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 + +#define tmp t0 +#define cfg t1 +#define icachesize t2 +#define ilinesize t3 +#define iways t4 +#define dcachesize t5 +#define dlinesize t6 +#define dways t7 +#define save_ra v1 + +#define INIT_L1_CACHE +#if defined(INIT_L1_CACHE) +.sdata; .globl __pic32_icache_size; .type __pic32_icache_size,@object; .size __pic32_icache_size,4; __pic32_icache_size:; .word -1 +.sdata; .globl __pic32_icache_linesize; .type __pic32_icache_linesize,@object; .size __pic32_icache_linesize,4; __pic32_icache_linesize:; .word -1 +.sdata; .globl __pic32_icache_ways; .type __pic32_icache_ways,@object; .size __pic32_icache_ways,4; __pic32_icache_ways:; .word 1 + +.sdata; .globl __pic32_dcache_size; .type __pic32_dcache_size,@object; .size __pic32_dcache_size,4; __pic32_dcache_size:; .word -1 +.sdata; .globl __pic32_dcache_linesize; .type __pic32_dcache_linesize,@object; .size __pic32_dcache_linesize,4; __pic32_dcache_linesize:; .word -1 +.sdata; .globl __pic32_dcache_ways; .type __pic32_dcache_ways,@object; .size __pic32_dcache_ways,4; __pic32_dcache_ways:; .word 1 + +.sdata; .globl __pic32_scache_size; .type __pic32_scache_size,@object; .size __pic32_scache_size,4; __pic32_scache_size:; .word -1 +.sdata; .globl __pic32_scache_linesize; .type __pic32_scache_linesize,@object; .size __pic32_scache_linesize,4; __pic32_scache_linesize:; .word -1 +.sdata; .globl __pic32_scache_ways; .type __pic32_scache_ways,@object; .size __pic32_scache_ways,4; __pic32_scache_ways:; .word 1 + +.section .cache_init.cache, code + .set nomips16 + .ent __size_cache; __size_cache: + mfc0 cfg,_CP0_CONFIG + + li icachesize,0 + li ilinesize,0 + li dcachesize,0 + li dlinesize,0 + + /* Check that we have Config1 */ + and tmp,cfg,_CP0_CONFIG_M_MASK + mfc0 cfg,_CP0_CONFIG1 + beqz tmp,9f + nop + + /* Get icache line size (log2) */ + and tmp,cfg,_CP0_CONFIG1_IL_MASK + srl tmp,_CP0_CONFIG1_IL_POSITION + beqz tmp,8f # no i-cache + addu tmp,1 + + /* Get number of icache ways */ + and iways,cfg,_CP0_CONFIG1_IA_MASK + srl iways,_CP0_CONFIG1_IA_POSITION + addu iways,1 + move icachesize,iways + + /* total icache size = lines/way * linesize *ways */ + li ilinesize,1 + sll ilinesize,tmp + sll icachesize,tmp + + /* get icache lines per way */ + and tmp,cfg,_CP0_CONFIG1_IS_MASK + srl tmp,_CP0_CONFIG1_IS_POSITION + addu tmp,6 + sll icachesize,tmp + + /* Get dcache line size (log2) */ +8: and tmp,cfg,_CP0_CONFIG1_DL_MASK + srl tmp,_CP0_CONFIG1_DL_POSITION + beqz tmp,8f # no d-cache + addu tmp,1 + + /* Get number of dcache ways */ + and dways,cfg,_CP0_CONFIG1_DA_MASK + srl dways,_CP0_CONFIG1_DA_POSITION + addu dways,1 + move dcachesize,dways + + /* Total dcache size = lines/way * linesize * ways */ + li dlinesize,1 + sll dlinesize,tmp + sll dcachesize,tmp + + and tmp,cfg,_CP0_CONFIG1_DS_MASK + srl tmp,_CP0_CONFIG1_DS_POSITION + addu tmp,6 + sll dcachesize,tmp + +#undef cfg +#undef tmp + +8: +9: j ra + nop + .size __size_cache,.-__size_cache; .end __size_cache; + +/* + * void __pic32_size_cache() + * + * Work out size of I & D caches (assume already initialized) + */ + .section .cache_init.pic32_size_cache, code + .set nomips16 + .globl __pic32_size_cache; .ent __pic32_size_cache; + +__pic32_size_cache: + lw t0,__pic32_icache_size + move a3,ra + bgtz t0,8f # already known? + + bal __size_cache + move ra,a3 + +..savesize: + sw icachesize,__pic32_icache_size + sw dcachesize,__pic32_dcache_size + sw ilinesize,__pic32_icache_linesize + sw dlinesize,__pic32_dcache_linesize + sw iways,__pic32_icache_ways + sw dways,__pic32_dcache_ways + +8: j ra + nop + .size __pic32_size_cache,.-__pic32_size_cache; .end __pic32_size_cache + +/* + * void __pic32_init_cache() + * + * Work out size and initialize I & D caches. + */ + .section .cache_init.pic32_init_cache, code + .set nomips16 + .globl __pic32_init_cache; .ent __pic32_init_cache; +__pic32_init_cache: + + move save_ra,ra + bal __size_cache + + /* Run uncached */ + .set noreorder + .set nomacro +#if 0 + bal 1f + # + li cfg,0xa0000000 +1: or cfg,ra + addu cfg,16 + jr cfg + move ra,v1 +#endif + + /* + * The caches may be in an indeterminate state, so we force an + * invalidate, load/fill, and invalidate for each line. + */ + + /* Disable all i/u and cache exceptions */ + .set macro + .set noreorder + # Disable interrupts and set UM=1 + # Save current status in tmp + mfc0 t0,_CP0_STATUS + li t1,~_CP0_STATUS_IE_MASK + and t1,t0 + or t1,_CP0_STATUS_ERL_MASK + mtc0 t1,_CP0_STATUS + ehb + + mtc0 zero,_CP0_ERRCTL + mtc0 zero,_CP0_TAGLO # 4K taglo / 2*K itaglo + ehb + + /* Initialize primary instruction cache */ + .set noreorder +4: la a0,__pic32_init_cache_program_base_addr + bne a0,zero,0f + /* Use a default if the symbol is not defined */ + li a0,0x9D000000 /* KSEG0_PROGRAM_BASE */ +0: beqz icachesize,8f # icachesize + addu a1,a0,icachesize # limit = base + icachesize +1: addu a0,ilinesize # line size + bne a0,a1,1b + cache Index_Store_Tag_I,-4(a0) # BDSLOT: clear tag + + + /* Initialize primary data cache */ + .set noreorder +8: la a0,__pic32_init_cache_data_base_addr + bne a0,zero,0f + /* Use a default if the symbol is not defined */ + li a0,0x80000000 /* KSEG_DATA_BASE */ + +0: beqz dcachesize,8f + addu a1,a0,dcachesize # limit = base + dcachesize +1: addu a0,dlinesize + bne a0,a1,1b + cache Index_Store_Tag_D,-4(a0) # BDSLOT: clear tag + + .set reorder + +8: sync + + /* Store the sizes only after the caches are initialized */ +4: sw icachesize,__pic32_icache_size + sw dcachesize,__pic32_dcache_size + sw ilinesize,__pic32_icache_linesize + sw dlinesize,__pic32_dcache_linesize + sw iways,__pic32_icache_ways + sw dways,__pic32_dcache_ways + + .set noreorder + + # restore status + mtc0 t0,_CP0_STATUS + ehb + + # Configure Cache Mode + mfc0 t1, _CP0_CONFIG + ori t1, _CP0_CONFIG_K0_MASK + xori t1, _CP0_CONFIG_K0_MASK + ori t1, __PIC32_CACHE_MODE + mtc0 t1, _CP0_CONFIG + ehb + + .set reorder + + move ra, save_ra + jr ra + nop + .size __pic32_init_cache,.-__pic32_init_cache; .end __pic32_init_cache; +#endif /* INIT_L1_CACHE */ + +#undef _CACHE_WRITEBACK_WRITEALLOCATE +#undef _CACHE_WRITETHROUGH_WRITEALLOCATE +#undef _CACHE_WRITETHROUGH_NOWRITEALLOCATE +#undef _CACHE_DISABLE + +#undef _CP0_ERRCTL +#undef _CP0_TAGLO http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/stubs/pic32_init_tlb_ebi_sqi.S ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/stubs/pic32_init_tlb_ebi_sqi.S b/kernel/os/src/arch/pic32/stubs/pic32_init_tlb_ebi_sqi.S new file mode 100644 index 0000000..045f5af --- /dev/null +++ b/kernel/os/src/arch/pic32/stubs/pic32_init_tlb_ebi_sqi.S @@ -0,0 +1,145 @@ +/*------------------------------------------------------------------------- + * + * Copyright (c) 2014, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its + * subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. Microchip's name may not be used to endorse or promote products + * derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *-------------------------------------------------------------------------*/ + +#include <xc.h> +#include <cp0defs.h> + +#define CFG1_MMUSSHIFT 25 + + .weak __pic32_tlb_init_values_count + .weak __pic32_tlb_init_values_begin + .weak __pic32_tlb_init_values_end + + .section .tlb.__pic32_tlb_init_ebi_sqi, code, keep + .set nomips16 + .set noreorder + + .global __pic32_tlb_init_ebi_sqi + .ent __pic32_tlb_init_ebi_sqi + +__pic32_tlb_init_ebi_sqi: + /* Determine if we have a TLB */ + /* Read C0 Config0 */ + mfc0 v1, _CP0_CONFIG + /* check MT field */ + ext v1, v1, 7, 3 + li a3, 0x1 + bne v1, a3, __done_init_tlb + + /* read C0 Config1 */ + mfc0 v0, _CP0_CONFIG1 + +__start_init_tlb: + /* Extract MMU Size */ + ext v1, v0, CFG1_MMUSSHIFT, 6 + + mtc0 zero, _CP0_ENTRYLO0 + mtc0 zero, _CP0_ENTRYLO1 + mtc0 zero, _CP0_PAGEMASK + mtc0 zero, _CP0_WIRED + + move a0, $0 + lui a0, 0x8000 + +__next_tlb_entry_pair: + mtc0 v1, _CP0_INDEX + mtc0 a0, _CP0_ENTRYHI + + ehb + tlbwi + + add a0, (2<<13) + add v1, -1 + bne v1, zero, __next_tlb_entry_pair + nop + + /* Get the count of the entries in the table from a linker-script symbol */ +__count_tlb_init_values: + lui a0, %hi(__pic32_tlb_init_values_count) + ori a0, %lo(__pic32_tlb_init_values_count) + +__device_tlb_entries: + /* Set lowest count (a0) TLB entries as fixed (entry 0 and entry 1) */ + mtc0 a0, _CP0_WIRED + + /* Point a1 to the beginning of the linker-script generated table */ + la a1, __pic32_tlb_init_values_begin + la a2, __pic32_tlb_init_values_end + move a3, zero /* index */ + + /* Loop through the tables until we have done the correct number of iterations. */ + /* When the current pointer (a1) points to the end of the table (a2) we are done. */ +1: + beq a1, a2, __done_init_tlb /* done */ + + /* Create one page table entry consisting of two 16MB physical pages */ + /* 16MB page mask for Entry 0 */ + lui t1,0x01FF /* in branch delay slot */ + ori t1,t1,0xE000 + + mtc0 t1, _CP0_PAGEMASK + + /* TLB entry index */ + mtc0 a3, _CP0_INDEX + + /* Each entry consists of three words */ + lw t0, 0(a1) /* ENTRYHI */ + lw t1, 4(a1) /* ENTRYLO0 */ + lw t2, 8(a1) /* ENTRYLO1 */ + + /* physical base address <31:12>, cacheable (write back), dirty, global set */ + /* First 32MB page in Entrylo0 */ + mtc0 t1, _CP0_ENTRYLO0 + + /* Second 32MB page in EntryLo1 */ + mtc0 t2, _CP0_ENTRYLO1 + + /* virtual base address (ASID 0) */ + mtc0 t0, _CP0_ENTRYHI + ehb + tlbwi + + /* Next entry */ + add a1, 12 /* Point to next entry (WORD_SIZE * 3) */ + add a3, 1 /* Increment index */ + b 1b + nop + +__done_init_tlb: + jr ra + nop + +.size __pic32_tlb_init_ebi_sqi,.-__pic32_tlb_init_ebi_sqi; .end __pic32_tlb_init_ebi_sqi; + http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0163ea6c/kernel/os/src/arch/pic32/stubs/sbrk.c ---------------------------------------------------------------------- diff --git a/kernel/os/src/arch/pic32/stubs/sbrk.c b/kernel/os/src/arch/pic32/stubs/sbrk.c new file mode 100644 index 0000000..a59f3c3 --- /dev/null +++ b/kernel/os/src/arch/pic32/stubs/sbrk.c @@ -0,0 +1,305 @@ +#ident "c/stubs/sbrk.c: Copyright (c) MIPS Technologies, Inc. All rights reserved." + +/* + * Unpublished work (c) MIPS Technologies, Inc. All rights reserved. + * Unpublished rights reserved under the copyright laws of the United + * States of America and other countries. + * + * This code is confidential and proprietary to MIPS Technologies, + * Inc. ("MIPS Technologies") and may be disclosed only as permitted in + * writing by MIPS Technologies. Any copying, reproducing, modifying, + * use or disclosure of this code (in whole or in part) that is not + * expressly permitted in writing by MIPS Technologies is strictly + * prohibited. At a minimum, this code is protected under trade secret, + * unfair competition, and copyright laws. Violations thereof may result + * in criminal penalties and fines. + * + * MIPS Technologies reserves the right to change this code to improve + * function, design or otherwise. MIPS Technologies does not assume any + * liability arising out of the application or use of this code, or of + * any error or omission in such code. Any warranties, whether express, + * statutory, implied or otherwise, including but not limited to the + * implied warranties of merchantability or fitness for a particular + * purpose, are excluded. Except as expressly provided in any written + * license agreement from MIPS Technologies, the furnishing of this + * code does not give recipient any license to any intellectual property + * rights, including any patent rights, that cover this code. + * + * This code shall not be exported, reexported, transferred, or released, + * directly or indirectly, in violation of the law of any country or + * international law, regulation, treaty, Executive Order, statute, + * amendments or supplements thereto. Should a conflict arise regarding + * the export, reexport, transfer, or release of this code, the laws of + * the United States of America shall be the governing law. + * + * This code may only be disclosed to the United States government + * ("Government"), or to Government users, with prior written consent + * from MIPS Technologies. This code constitutes one or more of the + * following: commercial computer software, commercial computer software + * documentation or other commercial items. If the user of this code, + * or any related documentation of any kind, including related technical + * data or manuals, is an agency, department, or other entity of the + * Government, the use, duplication, reproduction, release, modification, + * disclosure, or transfer of this code, or any related documentation + * of any kind, is restricted in accordance with Federal Acquisition + * Regulation 12.212 for civilian agencies and Defense Federal Acquisition + * Regulation Supplement 227.7202 for military agencies. The use of this + * code by the Government is further restricted in accordance with the + * terms of the license agreement(s) and/or applicable contract terms + * and conditions covering this code from MIPS Technologies. + * + * + */ + +/* + * sbrk.c: a generic sbrk() emulation. + */ + +#include <string.h> +#include <errno.h> + +#include <sys/kmem.h> + +/* memory layout */ +struct sbd_region { + _paddr_t base; + size_t size; + int type; +}; + +/* _minbrk and _maxbrk can be set by startup code, or by a linker + script, so we don't want them in bss where they'll get cleared, so + they can't be common, but they must be capable of being + overridden. */ +void * _minbrk __attribute__((weak)) = 0; +void * _maxbrk __attribute__((weak)) = 0; + +extern int errno; +extern char _end[]; + +#if 0 +static pthread_mutex_t sbmx = PTHREAD_MUTEX_INITIALIZER; +#endif + +static void * curbrk = 0; + +#ifndef MINHEAP +#define MINHEAP (1 * 1024) +#endif + +#ifndef MAXSTACK +#define MAXSTACK (32 * 1024) +#endif + +#ifndef PAGESIZE +#define PAGESIZE 128 +#endif + +#define SBD_MEM_END 0 +#define SBD_MEM_RAM 1 + +int +getpagesize () +{ + return PAGESIZE; +} + + +/* + * The _sbd_memlayout() function returns a pointer to a phys memory + * region table, but note that at present sbrk() only uses the first + * entry. + * + * This function can be overridden by the board-specific code + * if it has some other way to determine the real size of + * physical memory (e.g. reading the memory controller). + */ + +const struct sbd_region * _sbd_memlayout (void); +#pragma weak _sbd_memlayout=_stub_sbd_memlayout +const struct sbd_region *_stub_sbd_memlayout (void); + +const struct sbd_region * +_stub_sbd_memlayout (void) +{ + static struct sbd_region mem[2]; + extern char _heap[]; + extern char _min_heap_size[]; + + mem[0].type = SBD_MEM_RAM; + mem[0].base = (_paddr_t)(&_heap); + mem[0].size = (size_t)(&_min_heap_size); + + return mem; +} + + +/* + * Initialise the sbrk heap. + * + * This function is hard-wired to the idea that the code is linked to + * KSEG0 or KSEG1 addresses. It could just about cope with being + * linked to run in KUSEG, as long as there's a one-to-one mapping + * from virtual to physical address. If you are playing real virtual + * memory games then the functions in the module will have to be + * replaced. + */ + +void +_sbrk_init (void) +{ + const struct sbd_region * layout; + void * minva, * maxva; + _paddr_t rbase, rtop, min, max; + extern char _heap[]; + extern char _min_heap_size[]; + + if (curbrk) + return; + + if (_minbrk) + /* user specified heap start */ + minva = _minbrk; + else + /* usually heap starts after data & bss segment */ +#if (__C32_VERSION__ > 200) + minva = &_heap; +#else + minva = _end; +#endif + + if (_maxbrk) + /* user specified heap top */ + maxva = _maxbrk; + else { + /* usually stack is at top of memory, and + heap grows up towards base of stack */ +#if (__C32_VERSION__ > 200) + maxva = (void*)(&_heap) + (size_t)(&_min_heap_size); +#else + char * sp; + __asm__ ("move %0,$sp" : "=d" (sp)); + maxva = sp - MAXSTACK; +#endif + } + + /* convert min/max to physical addresses */ + if (IS_KVA01 (minva)) + min = KVA_TO_PA (minva); + else + /* use virtual address */ + min = (_paddr_t) minva; + + if (IS_KVA01 (maxva)) + max = KVA_TO_PA (maxva); + else + max = (_paddr_t) maxva; + + /* determine physical memory layout */ + layout = _sbd_memlayout (); + + /* base of heap must be inside memory region #0 */ + rbase = layout[0].base; + rtop = rbase + layout[0].size; + if (min < rbase || min >= rtop) { + if (rbase >= KVA_TO_PA (_end)) + /* no overlap of region with data - use region base */ + min = rbase; + else + /* can't determine a good heap base */ + /* XXX could try _end in case of bad _minbrk setting */ + return; + } + + /* end of heap must be inside memory region #0 (and above base) */ + if (max < min || max >= rtop) { + if (rtop > min) + /* use top of region as top of heap */ + /* XXX what about poss overlap with stack? */ + max = rtop; + else + /* can't determine a good heap top */ + return; + } + + /* put minbrk/maxbrk in same kernel virtual segment as data */ + if (IS_KVA1 (_end)) { + /* kseg1: uncached data segment */ + _minbrk = PA_TO_KVA1 (min); + _maxbrk = PA_TO_KVA1 (max); + } + else if (IS_KVA0 (_end)) { + /* kseg0: cached data segmnt */ + _minbrk = PA_TO_KVA0 (min); + _maxbrk = PA_TO_KVA0 (max); + } + else { + /* kuseg: use virtual addresses */ + _minbrk = (void *) min; + _minbrk = (void *) max; + } + + curbrk = _minbrk; +} + + +void * +_sbrk (int n) +{ + void *newbrk, *p; + +#if 0 + pthread_mutex_lock (&sbmx); +#endif + if (!curbrk) { + _sbrk_init (); + if (!curbrk) { + errno = ENOMEM; +#if 0 + pthread_mutex_unlock (&sbmx); +#endif + return (void *)-1; + } + } + + p = curbrk; + newbrk = curbrk + n; + if (n > 0) { + if (newbrk < curbrk || newbrk > _maxbrk) { + errno = ENOMEM; +#if 0 + pthread_mutex_unlock (&sbmx); +#endif + return (void *)-1; + } + } else { + if (newbrk > curbrk || newbrk < _minbrk) { + errno = EINVAL; +#if 0 + pthread_mutex_unlock (&sbmx); +#endif + return (void *)-1; + } + } + curbrk = newbrk; + +#if 0 + pthread_mutex_unlock (&sbmx); +#endif + + return p; +} + +void * +sbrk (int n) +{ + void *p; + + p = _sbrk(n); + + /* sbrk defined to return zeroed pages */ + if ((n > 0) && (p != (void *)-1)) + memset (p, 0, n); + + return p; +}