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from 436c17f885 [HEXAGON][TOPI] This PR adjusts schedules so >64 length vector loads/stores are not generated at LLVM level. This is a workaround for an instruction selection issue in current version of llvm for hexagon (#12471) add e140a27495 [COMMUNITY] Adam Straw -> Reviewer (#12480) No new revisions were added by this update. Summary of changes: CONTRIBUTORS.md | 1 + 1 file changed, 1 insertion(+)